Tweak docs

README.md

@@ -19,7 +19,7 @@ Ergonomic hardware definition language that compiles to Verilog.
 * Structs
 * Column accurate compile error reporting
 
-[Learn more about these features](docs/feature_overview.md).
+[Learn more about these features](docs/feature_overview.md)
 
 ## Example
 
@@ -43,7 +43,7 @@ What does Wyre look like? Here is a basic example design with 2 modules, a clock
 
 ## Background
 
-A while back I got a Lattice iCE40 FPGA to learn more about how computers work at a low level. I've had a lot of fun making designs for it in Verilog. During the process I kept track of gripes with the toolchain, and ended up with a list of mostly minor things, but nonetheless a list that had a fair amount of items. I felt that there were enough to justify building some new tooling, and Wyre is the result.
+A while back I got a Lattice iCE40 FPGA to learn more about how computers work at a low level. I've had a lot of fun making designs for it in Verilog. During the process I kept track of gripes with the toolchain. I ended up with a list of mostly minor things, but nonetheless a list that had a fair amount of items. I felt that there were enough items to justify building some new tooling, and Wyre is the result.
 
 Compared to Verilog, Wyre aims to cut down on verbosity, improve design iteration speed and reduce errors (via strong typing). Wyre compiles to Verilog, so any design can be fed through an existing Verilog-based toolchain.
 
@@ -63,7 +63,7 @@ You can also view [more examples](examples).
 
 ## Roadmap
 
-Feedback is welcome! If you have ideas for new features or for improving existing features, let me know [by creating an issue](TODO).
+Feedback is welcome! If you have ideas for new features or for improving existing features, let me know [by creating an issue](https://github.com/nickmqb/wyre/issues).
 
 ## Twitter
 

docs/feature_overview.md

@@ -25,7 +25,7 @@ Modules can be instantiated inline. Example:
 		// ...
 	}
 
-Assuming that `adder` has two outputs `val` and `c_out`, they can be accessed as `sum.val` and `sum.c_out`. There is no need to explicitly connect any output wires.
+If we imagine that `adder` has two outputs `val` and `c_out`, they can be accessed as `sum.val` and `sum.c_out`. There is no need to explicitly connect any output wires.
 
 ### Order independent declarations
 

docs/getting_started.md

@@ -15,7 +15,7 @@ You can choose between the following two options:
 	* MSVC: `cl /Zi wyre.c`
 1. You now have a Wyre compiler!
 
-### From .c
+### From .c source
 
 If you prefer to not install Muon, you can take a shortcut:
 
@@ -36,7 +36,7 @@ Supported flags:
 
 * `--output [path]`. The output of the compiler, a Verilog file.
 * `--top [module]`. Name of the topmost module in the design.
-* `--indent [n]`. Tab size, in spaces ([learn more about significant whitespace](language_tour.md)). Set to 0 to ignore.
+* `--indent [n]`. Tab size, in spaces ([learn more about significant whitespace](language_guide.md)). Set to 0 to ignore.
 * `--max-errors [n]`. Maximum number of compile errors to display.
 
 To compile the [led](../examples/led.w) example:

examples/features.w

@@ -60,7 +60,7 @@ some_module(clk $1, a $4, b $4) {
 	inverted := ~a
 	extended_wire $32 := zx a // a is zero extended to 32 bits total
 
-	// Binary operators: + - & | ^ ==  << >>
+	// Binary operators
 	op_add := a + b
 	op_subtract := a - b
 	op_and := a & b
@@ -120,6 +120,8 @@ another_module(
 	#part_b := chunk(#sw, 1, 2)
 }
 
+// Note: as you can see above, module inputs can be separated by newlines if you prefer. This also works for module instantiations.
+
 // Constants are global, and must be declared outside a module
 some_constant $10 := 100
 some_constant2 := 100 // Can omit type if you prefer
@@ -131,5 +133,3 @@ SB_GB blackbox(
 	// Outputs are declared inside module body
 	out GLOBAL_BUFFER_OUTPUT $1
 }
-
-// Note: as you can see above, module inputs can be separated by newlines if you prefer. This also works for module instantiations.