Fix bugs

compiler/emulator.mu

@@ -73,6 +73,8 @@ Emulator {
 			stack: new List<Value>{},
 		}
 		
+		s.stack.reserve(256)
+
 		EmulatorAllocator.top(s, top)
 		
 		commitValues(s)
@@ -288,9 +290,9 @@ EmulatorStep {
 				emiti(s, Opcode.load, si)
 			}
 			AssignStatement: {
-				si := s.inst.localState[node.localId] + max(s.evalCtxField, 0)
+				si := s.inst.localState[node.localId]
 				if si >= 0 {
-					emiti(s, Opcode.load, si)
+					emiti(s, Opcode.load, si + max(s.evalCtxField, 0))
 				} else {
 					expression(s, node.expr)
 				}

compiler/type_checker.mu

@@ -175,6 +175,8 @@ TypeChecker {
 
 	ensureStructDone(s TypeCheckerState, def StructDef) {
 		if def.flags & StructFlags.typeCheckDone != 0 {
+			// OK
+		} else {
 			prev := pushContext(s, def.unit, null)
 			struct_(s, def)
 			restoreContext(s, prev)

compiler/verilog_generator.mu

@@ -73,6 +73,7 @@ VerilogGenerator {
 		s.globals.add("inout")
 		s.globals.add("case")
 		s.globals.add("signed")
+		s.globals.add("cell")
 
 		for u in s.comp.units {
 			for node in u.contents {