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278 lines
8.1 KiB
C
278 lines
8.1 KiB
C
/* prmci3.c: MUTATOR CONTEXT (INTEL 386)
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*
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* $Id$
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* Copyright (c) 2001-2020 Ravenbrook Limited. See end of file for license.
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*
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* .design: See <design/prmc> for the generic design of the interface
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* which is implemented in this module, including the contracts for the
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* functions.
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*
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* .purpose: Implement the mutator context module. <design/prmc>.
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*
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* .requirements: Current requirements are for limited support only, for
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* stepping the sorts of instructions that the Dylan compiler might
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* generate for table vector access - i.e., a restricted subset of MOV
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* addressing modes. This avoids the need to scan entire weak tables at
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* an inappropriate rank when a page fault occurs.
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*
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*
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* SOURCES
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*
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* .source.i486: Intel486 Microprocessor Family Programmer's
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* Reference Manual
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*
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* .source.dylan: Dylan table code implementation. Especially the
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* following HOPE units:
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* D-lib-dylan!table.dylan (class <entry-vector>, slot entry-element)
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* D-dfmc-harp-cg!harp-primitives.dylan (method op--repeated-slot-element)
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* D-harp-pentium-harp!moves.dylan (pentium-template ld-index)
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*
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*
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* ASSUMPTIONS
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*
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* .assume.null: It's always safe for MutatorContextCanStepInstruction
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* to return FALSE. A null implementation of this module would be
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* overly conservative but otherwise correct.
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*
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* .assume.want: The Dylan implementation is likely to access a
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* weak table vector using either MOV r/m32,r32 or MOV r32,r/m32
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* instructions, where the r/m32 operand will be of one of the forms
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* disp8[reg], disp8[reg1][reg2], disp8[reg1][reg2*4] (see .source.dylan
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* and .source.i486)
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*
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* .assume.i3: Assume the following about the i386 environment:
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* Steppable instructions (.assume.want) use the CS, DS & SS
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* segment registers only (see .source.i486 Table 2-3).
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* The processor runs in 32 bit mode.
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* The CS, DS and SS segment registers all describe identical 32-
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* bit flat address spaces.
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*/
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#include "mpm.h"
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#include "prmci3.h"
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SRCID(prmci3, "$Id$");
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#if !defined(MPS_ARCH_I3)
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#error "prmci3.c is specific to MPS_ARCH_I3"
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#endif
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/* DecodeCB -- Decode an Intel x86 control byte into Hi, Medium & Low fields */
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static void DecodeCB(unsigned int *hReturn,
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unsigned int *mReturn,
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unsigned int *lReturn,
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Byte op)
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{
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/* see .source.i486 Figure 26-2 */
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unsigned int uop = (unsigned int)op;
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*lReturn = uop & 7;
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uop = uop >> 3;
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*mReturn = uop & 7;
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uop = uop >> 3;
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*hReturn = uop & 3;
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}
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/* DecodeSIB -- Decode a Scale Index Base byte for an Intel x86 instruction */
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static void DecodeSIB(unsigned int *sReturn,
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unsigned int *iReturn,
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unsigned int *bReturn,
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Byte op)
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{
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DecodeCB(sReturn, iReturn, bReturn, op);
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}
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/* DecodeModRM -- Decode a ModR/M byte for an Intel x86 instruction */
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static void DecodeModRM(unsigned int *modReturn,
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unsigned int *rReturn,
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unsigned int *mReturn,
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Byte op)
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{
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DecodeCB(modReturn, rReturn, mReturn, op);
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}
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/* RegValue -- Return the value of a machine register from a context */
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static Word RegValue(MutatorContext context, unsigned int regnum)
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{
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MRef addr;
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addr = Prmci3AddressHoldingReg(context, regnum);
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return *addr;
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}
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/* Return a byte element of an instruction vector as a
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* Word value, with sign extension
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*/
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static Word SignedInsElt(Byte insvec[], Count i)
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{
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signed char eltb;
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eltb = ((signed char*)insvec)[i];
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return (Word)eltb;
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}
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/* If a MOV instruction is a sufficiently simple example of a
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* move between a register and memory (in either direction),
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* then find the register, the effective address and the size
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* of the instruction. The instruction is considered sufficiently
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* simple if it uses a single byte displacement, a base register,
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* and either no index or a (possibly scaled) register.
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*/
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static Bool DecodeSimpleMov(unsigned int *regnumReturn,
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MRef *memReturn,
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Size *inslenReturn,
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MutatorContext context,
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Byte insvec[])
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{
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unsigned int mod;
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unsigned int r;
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unsigned int m;
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DecodeModRM(&mod, &r, &m, insvec[1]); /* .source.i486 Table 26-3 */
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if(1 == mod) {
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/* Only know about single byte displacements, .assume.want */
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Word base;
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Word idx; /* can't shadow index(3) */
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Word disp;
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if(4 == m) {
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/* There is an index. */
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unsigned int s;
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unsigned int i;
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unsigned int b;
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DecodeSIB(&s, &i, &b, insvec[2]); /* .source.i486 Table 26-3 */
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if(4 == i) {
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return FALSE; /* degenerate SIB form - unused by Dylan compiler */
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}
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disp = SignedInsElt(insvec, 3);
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base = RegValue(context, b);
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idx = RegValue(context, i) << s;
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*inslenReturn = 4;
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} else {
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/* MOV with reg1 & [reg2+byte] parameters */
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disp = SignedInsElt(insvec, 2);
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base = RegValue(context, m);
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idx = 0;
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*inslenReturn = 3;
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}
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*regnumReturn = r;
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*memReturn = (MRef)(base + idx + disp); /* .assume.i3 */
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return TRUE;
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}
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return FALSE;
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}
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static Bool IsSimpleMov(Size *inslenReturn,
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MRef *srcReturn,
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MRef *destReturn,
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MutatorContext context)
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{
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Byte *insvec;
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unsigned int regnum;
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MRef mem;
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MRef faultmem;
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Prmci3DecodeFaultContext(&faultmem, &insvec, context);
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/* .assume.want */
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/* .source.i486 Page 26-210 */
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if((Byte)0x8b == insvec[0]) {
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/* This is an instruction of type MOV reg, r/m32 */
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if(DecodeSimpleMov(®num, &mem, inslenReturn, context, insvec)) {
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AVER(faultmem == mem); /* Ensure computed address matches exception */
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*srcReturn = mem;
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*destReturn = Prmci3AddressHoldingReg(context, regnum);
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return TRUE;
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}
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} else if((Byte)0x89 == insvec[0]) {
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/* This is an instruction of type MOV r/m32, reg */
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if(DecodeSimpleMov(®num, &mem, inslenReturn, context, insvec)) {
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AVER(faultmem == mem); /* Ensure computed address matches exception */
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*destReturn = mem;
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*srcReturn = Prmci3AddressHoldingReg(context, regnum);
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return TRUE;
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}
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}
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return FALSE;
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}
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Bool MutatorContextCanStepInstruction(MutatorContext context)
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{
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Size inslen;
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MRef src;
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MRef dest;
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AVERT(MutatorContext, context);
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/* .assume.null */
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/* .assume.want */
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if(IsSimpleMov(&inslen, &src, &dest, context)) {
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return TRUE;
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}
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return FALSE;
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}
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Res MutatorContextStepInstruction(MutatorContext context)
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{
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Size inslen;
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MRef src;
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MRef dest;
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AVERT(MutatorContext, context);
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/* .assume.null */
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/* .assume.want */
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if(IsSimpleMov(&inslen, &src, &dest, context)) {
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*dest = *src;
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Prmci3StepOverIns(context, inslen);
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return ResOK;
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}
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return ResUNIMPL;
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}
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/* C. COPYRIGHT AND LICENSE
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*
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* Copyright (C) 2001-2020 Ravenbrook Limited <http://www.ravenbrook.com/>.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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* IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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