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Sync with upstream verilog-mode revision c075a492
* lisp/progmodes/verilog-mode.el (verilog-mode-version): Bump. (verilog-menu): Add AUTOINSERTLAST. (verilog-no-indent-begin-re): When `verilog-indent-begin-after-if' is nil, fix indenting initial/final to match always statements, bug825. Reported by Tim Clapp. (verilog-extended-complete-re): Fix indentation of DPI-C imports, bug557. Reported by ZeDong Mao and Jason Forkey. (verilog-read-decls): Fix parsing typed interfaces. Fix AUTOINOUTMODPORT missing types. Reported by Stephan Bourduas. (verilog-auto-arg-ports): Fix verilog-auto-arg-format single. (verilog-auto-output-every): Add regexp to AUTOOUTPUTEVERY, bug793. Reported by Pierre-David Pfister. (verilog-auto-insert-lisp): Doc fix. (verilog-auto-insert-last, verilog-auto): Add AUTOINSERTLAST to allow post-AUTO user fixups, bug826. Reported by Dennis Muhlestein. (verilog-sk-ovm-class, verilog-sk-uvm-object) (verilog-sk-uvm-component): Fix missing string keyword in class skeletons, bug824. Reported by eldad faruhi.
This commit is contained in:
Wilson Snyder
Glenn Morris
parent
83f046769b
commit
dd7023e4f7
2 changed files with 76 additions and 14 deletions
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@ -1,3 +1,25 @@
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2014-10-07 Wilson Snyder <wsnyder@wsnyder.org>
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Sync with upstream verilog-mode revision c075a492.
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* progmodes/verilog-mode.el (verilog-mode-version): Bump.
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(verilog-menu): Add AUTOINSERTLAST.
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(verilog-no-indent-begin-re): When `verilog-indent-begin-after-if'
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is nil, fix indenting initial/final to match always statements, bug825.
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Reported by Tim Clapp.
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(verilog-extended-complete-re): Fix indentation of DPI-C imports,
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bug557. Reported by ZeDong Mao and Jason Forkey.
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(verilog-read-decls): Fix parsing typed interfaces.
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Fix AUTOINOUTMODPORT missing types. Reported by Stephan Bourduas.
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(verilog-auto-arg-ports): Fix verilog-auto-arg-format single.
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(verilog-auto-output-every): Add regexp to AUTOOUTPUTEVERY, bug793.
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Reported by Pierre-David Pfister.
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(verilog-auto-insert-lisp): Doc fix.
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(verilog-auto-insert-last, verilog-auto): Add AUTOINSERTLAST to
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allow post-AUTO user fixups, bug826. Reported by Dennis Muhlestein.
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(verilog-sk-ovm-class, verilog-sk-uvm-object)
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(verilog-sk-uvm-component): Fix missing string keyword in class
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skeletons, bug824. Reported by eldad faruhi.
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2014-10-06 Stefan Monnier <monnier@iro.umontreal.ca>
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* term/w32-win.el: Move all code from 32-common-fns.el here.
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@ -123,7 +123,7 @@
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;;; Code:
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;; This variable will always hold the version number of the mode
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(defconst verilog-mode-version "2014-05-31-3cd8144-vpo"
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(defconst verilog-mode-version "2014-10-03-c075a49-vpo"
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"Version of this Verilog mode.")
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(defconst verilog-mode-release-emacs t
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"If non-nil, this version of Verilog mode was released with Emacs itself.")
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@ -1474,6 +1474,8 @@ If set will become buffer local.")
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:help "Help on AUTOINPUT - adding inputs from cells"]
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["AUTOINSERTLISP" (describe-function 'verilog-auto-insert-lisp)
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:help "Help on AUTOINSERTLISP - insert text from a lisp function"]
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["AUTOINSERTLAST" (describe-function 'verilog-auto-insert-last)
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:help "Help on AUTOINSERTLISPLAST - insert text from a lisp function"]
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["AUTOINST" (describe-function 'verilog-auto-inst)
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:help "Help on AUTOINST - adding pins for cells"]
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["AUTOINST (.*)" (describe-function 'verilog-auto-star)
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@ -2265,7 +2267,10 @@ find the errors."
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;; "\\(assert\\|assume\\|cover\\)\\s-+property\\>"
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(defconst verilog-no-indent-begin-re
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"\\<\\(if\\|else\\|while\\|for\\|repeat\\|always\\|always_comb\\|always_ff\\|always_latch\\)\\>")
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(eval-when-compile
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(verilog-regexp-words
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'( "if" "else" "while" "for" "repeat" "always" "always_comb" "always_ff" "always_latch"
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"initial" "final"))))
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(defconst verilog-ends-re
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;; Parenthesis indicate type of keyword found
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@ -2719,9 +2724,9 @@ find the errors."
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(defconst verilog-disable-fork-re "\\(disable\\|wait\\)\\s-+fork\\>")
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(defconst verilog-extended-case-re "\\(\\(unique0?\\s-+\\|priority\\s-+\\)?case[xz]?\\)")
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(defconst verilog-extended-complete-re
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(concat "\\(\\(\\<extern\\s-+\\|\\<\\(\\<pure\\>\\s-+\\)?virtual\\s-+\\|\\<protected\\s-+\\)*\\(\\<function\\>\\|\\<task\\>\\)\\)"
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(concat "\\(\\(\\<extern\\s-+\\|\\<\\(\\<\\(pure\\|context\\)\\>\\s-+\\)?virtual\\s-+\\|\\<protected\\s-+\\)*\\(\\<function\\>\\|\\<task\\>\\)\\)"
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"\\|\\(\\(\\<typedef\\>\\s-+\\)*\\(\\<struct\\>\\|\\<union\\>\\|\\<class\\>\\)\\)"
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"\\|\\(\\(\\<import\\>\\s-+\\)?\\(\"DPI-C\"\\s-+\\)?\\(\\<pure\\>\\s-+\\)?\\(function\\>\\|task\\>\\)\\)"
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"\\|\\(\\(\\<import\\>\\s-+\\)?\\(\"DPI-C\"\\s-+\\)?\\(\\<\\(pure\\|context\\)\\>\\s-+\\)?\\([A-Za-z_][A-Za-z0-9_]*\\s-+=\\s-+\\)?\\(function\\>\\|task\\>\\)\\)"
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"\\|" verilog-extended-case-re ))
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(defconst verilog-basic-complete-re
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(eval-when-compile
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@ -8258,7 +8263,8 @@ Return an array of [outputs inouts inputs wire reg assign const]."
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(setq typedefed
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(if typedefed (concat typedefed " " keywd) keywd)))
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(t (setq vec nil enum nil rvalue nil signed nil
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typedefed nil multidim nil sig-paren paren
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typedefed keywd ; Have a type
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multidim nil sig-paren paren
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expect-signal 'sigs-var modport nil))))
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;; Interface with optional modport in v2k arglist?
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;; Skip over parsing modport, and take the interface name as the type
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@ -10650,6 +10656,7 @@ Takes SIGS list, adds MESSAGE to front and inserts each at INDENT-PT."
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(indent-to indent-pt)
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(while sigs
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(cond ((equal verilog-auto-arg-format 'single)
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(insert space)
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(indent-to indent-pt)
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(setq space "\n"))
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;; verilog-auto-arg-format 'packed
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@ -11816,10 +11823,18 @@ Typing \\[verilog-auto] will make this into:
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wire tempa = i;
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wire tempb = tempa;
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wire o = tempb;
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endmodule"
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endmodule
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You may also provide an optional regular expression, in which case only
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signals matching the regular expression will be included. For example the
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same expansion will result from only extracting outputs starting with ov:
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/*AUTOOUTPUTEVERY(\"^ov\")*/"
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(save-excursion
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;;Point must be at insertion point
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(let* ((indent-pt (current-indentation))
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(params (verilog-read-auto-params 0 1))
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(regexp (nth 0 params))
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(v2k (verilog-in-paren-quick))
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(modi (verilog-modi-current))
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(moddecls (verilog-modi-get-decls modi))
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@ -11827,6 +11842,11 @@ Typing \\[verilog-auto] will make this into:
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(verilog-signals-not-in
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(verilog-decls-get-signals moddecls)
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(verilog-decls-get-ports moddecls)))))
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(when regexp
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(setq sig-list (verilog-signals-matching-regexp
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sig-list regexp)))
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(setq sig-list (verilog-signals-not-matching-regexp
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sig-list verilog-auto-output-ignore-regexp))
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(verilog-forward-or-insert-line)
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(when v2k (verilog-repair-open-comma))
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(when sig-list
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@ -12417,9 +12437,13 @@ driver/monitor using AUTOINST in the testbench."
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(defun verilog-auto-insert-lisp ()
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"Expand AUTOINSERTLISP statements, as part of \\[verilog-auto].
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The Lisp code provided is called, and the Lisp code calls
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`insert` to insert text into the current file beginning on the
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line after the AUTOINSERTLISP.
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The Lisp code provided is called before other AUTOS are expanded,
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and the Lisp code generally will call `insert` to insert text
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into the current file beginning on the line after the
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AUTOINSERTLISP.
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See also AUTOINSERTLAST and `verilog-auto-insert-last' which
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executes after (as opposed to before) other AUTOs.
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See also AUTO_LISP, which takes a Lisp expression and evaluates
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it during `verilog-auto-inst' but does not insert any text.
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@ -12476,6 +12500,20 @@ text:
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(setq verilog-scan-cache-tick nil) ;; Clear cache; inserted unknown text
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(verilog-delete-empty-auto-pair))))
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(defun verilog-auto-insert-last ()
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"Expand AUTOINSERTLAST statements, as part of \\[verilog-auto].
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The Lisp code provided is called after all other AUTOS have been
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expanded, and the Lisp code generally will call `insert` to
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insert text into the current file beginning on the line after the
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AUTOINSERTLAST.
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Other than when called (after AUTOs are expanded), the functionality
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is otherwise identical to AUTOINSERTLISP and `verilog-auto-insert-lisp' which
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executes before (as opposed to after) other AUTOs.
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See `verilog-auto-insert-lisp' for examples."
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(verilog-auto-insert-lisp))
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(defun verilog-auto-sense-sigs (moddecls presense-sigs)
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"Return list of signals for current AUTOSENSE block."
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(let* ((sigss (verilog-read-always-signals))
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@ -13202,6 +13240,7 @@ Using \\[describe-function], see also:
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`verilog-auto-inout-param' for AUTOINOUTPARAM copying params from elsewhere
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`verilog-auto-input' for AUTOINPUT making hierarchy inputs
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`verilog-auto-insert-lisp' for AUTOINSERTLISP insert code from lisp function
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`verilog-auto-insert-last' for AUTOINSERTLAST insert code from lisp function
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`verilog-auto-inst' for AUTOINST instantiation pins
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`verilog-auto-star' for AUTOINST .* SystemVerilog pins
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`verilog-auto-inst-param' for AUTOINSTPARAM instantiation params
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@ -13278,7 +13317,6 @@ Wilson Snyder (wsnyder@wsnyder.org)."
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(verilog-inject-arg))
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;;
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;; Do user inserts first, so their code can insert AUTOs
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;; We may provide an AUTOINSERTLISPLAST if another cleanup pass is needed
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(verilog-auto-re-search-do "/\\*AUTOINSERTLISP(.*?)\\*/"
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'verilog-auto-insert-lisp)
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;; Expand instances before need the signals the instances input/output
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@ -13312,11 +13350,13 @@ Wilson Snyder (wsnyder@wsnyder.org)."
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(verilog-auto-re-search-do "/\\*AUTOREG\\*/" 'verilog-auto-reg)
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(verilog-auto-re-search-do "/\\*AUTOREGINPUT\\*/" 'verilog-auto-reg-input)
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;; outputevery needs AUTOOUTPUTs done first
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(verilog-auto-re-search-do "/\\*AUTOOUTPUTEVERY\\*/" 'verilog-auto-output-every)
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(verilog-auto-re-search-do "/\\*AUTOOUTPUTEVERY\\((.*?)\\)?\\*/" 'verilog-auto-output-every)
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;; After we've created all new variables
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(verilog-auto-re-search-do "/\\*AUTOUNUSED\\*/" 'verilog-auto-unused)
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;; Must be after all inputs outputs are generated
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(verilog-auto-re-search-do "/\\*AUTOARG\\*/" 'verilog-auto-arg)
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;; User inserts
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(verilog-auto-re-search-do "/\\*AUTOINSERTLAST(.*?)\\*/" 'verilog-auto-insert-last)
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;; Fix line numbers (comments only)
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(when verilog-auto-inst-template-numbers
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(verilog-auto-templated-rel))
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@ -13485,7 +13525,7 @@ See also `verilog-header' for an alternative format."
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> "`ovm_object_utils_begin(" name ")" \n
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> (- verilog-indent-level) " `ovm_object_utils_end" \n
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> _ \n
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> "function new(name=\"" name "\");" \n
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> "function new(string name=\"" name "\");" \n
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> "super.new(name);" \n
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> (- verilog-indent-level) "endfunction" \n
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> _ \n
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@ -13499,7 +13539,7 @@ See also `verilog-header' for an alternative format."
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> "`uvm_object_utils_begin(" name ")" \n
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> (- verilog-indent-level) "`uvm_object_utils_end" \n
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> _ \n
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> "function new(name=\"" name "\");" \n
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> "function new(string name=\"" name "\");" \n
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> "super.new(name);" \n
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> (- verilog-indent-level) "endfunction" \n
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> _ \n
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@ -13513,7 +13553,7 @@ See also `verilog-header' for an alternative format."
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> "`uvm_component_utils_begin(" name ")" \n
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> (- verilog-indent-level) "`uvm_component_utils_end" \n
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> _ \n
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> "function new(name=\"\", uvm_component parent);" \n
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> "function new(string name=\"\", uvm_component parent);" \n
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> "super.new(name, parent);" \n
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> (- verilog-indent-level) "endfunction" \n
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> _ \n
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