Sync with upstream verilog-mode revision aa4b777

* lisp/progmodes/verilog-mode.el (verilog-mode-version): Update.
(verilog-auto-end-comment-lines-re, verilog-end-block-ordered-re)
(verilog-set-auto-endcomments): Automatically comment property/
endproperty blocks to match other similar blocks like sequence/
endsequence, function/endfunction, etc.  Reported by Alex Reed.
(verilog-set-auto-endcomments): Fix end comments for functions of
type void, etc.  Detect the function- or task-name when
auto-commenting blocks that lack an explicit portlist.
Reported by Alex Reed.
(verilog-nameable-item-re): Fix nameable items that can have an
end-identifier to include endchecker, endgroup, endprogram,
endproperty, and endsequence.  Reported by Alex Reed.
(verilog-preprocessor-re, verilog-beg-of-statement):
Fix indentation of property/endproperty around pre-processor
directives.  Reported by Alex Reed.
(verilog-label-be): When auto-commenting a buffer, consider
auto-comments on all known keywords (not just a subset thereof).
Reported by Alex Reed.
(verilog-beg-of-statement): Fix labeling do-while blocks, bug842.
Reported by Alex Reed.
(verilog-beg-of-statement-1, verilog-at-constraint-p):
Fix hanging with many curly-bracket pairs, bug663.
(verilog-do-indent): Fix electric tab deleting form-feeds.
Note caused by indent-line-to deleting tabls pre 24.5.
(verilog-auto-output, verilog-auto-input, verilog-auto-inout)
(verilog-auto-inout-module, verilog-auto-inout-in): Doc fixes.
(verilog-read-always-signals, verilog-auto-sense-sigs)
(verilog-auto-reset): Fix AUTORESET with always_comb and always_latch,
bug844.  Reported by Greg Hilton.

Author: Alex Reed <acreed4@gmail.com> (tiny change)
* lisp/progmodes/verilog-mode.el (verilog-no-indent-begin-re):
Fix `verilog-indent-begin-after-if' nil not honoring 'forever',
'foreach', and 'do' keywords.
(verilog-endcomment-reason-re, verilog-beg-of-statement):
Fix labeling do-while blocks, bug842.
(verilog-backward-token): Fix indenting sensitivity lists with named
events, bug840.

lisp/ChangeLog

@@ -1,3 +1,46 @@
+2014-12-09  Wilson Snyder  <wsnyder@wsnyder.org>
+
+	Sync with upstream verilog-mode revision aa4b777.
+	* progmodes/verilog-mode.el (verilog-mode-version): Update.
+	(verilog-auto-end-comment-lines-re, verilog-end-block-ordered-re)
+	(verilog-set-auto-endcomments): Automatically comment property/
+	endproperty blocks to match other similar blocks like sequence/
+	endsequence, function/endfunction, etc.  Reported by Alex Reed.
+	(verilog-set-auto-endcomments): Fix end comments for functions of
+	type void, etc.  Detect the function- or task-name when
+	auto-commenting blocks that lack an explicit portlist.
+	Reported by Alex Reed.
+	(verilog-nameable-item-re): Fix nameable items that can have an
+	end-identifier to include endchecker, endgroup, endprogram,
+	endproperty, and endsequence.  Reported by Alex Reed.
+	(verilog-preprocessor-re, verilog-beg-of-statement):
+	Fix indentation of property/endproperty around pre-processor
+	directives.  Reported by Alex Reed.
+	(verilog-label-be): When auto-commenting a buffer, consider
+	auto-comments on all known keywords (not just a subset thereof).
+	Reported by Alex Reed.
+	(verilog-beg-of-statement): Fix labeling do-while blocks, bug842.
+	Reported by Alex Reed.
+	(verilog-beg-of-statement-1, verilog-at-constraint-p):
+	Fix hanging with many curly-bracket pairs, bug663.
+	(verilog-do-indent): Fix electric tab deleting form-feeds.
+	Note caused by indent-line-to deleting tabls pre 24.5.
+	(verilog-auto-output, verilog-auto-input, verilog-auto-inout)
+	(verilog-auto-inout-module, verilog-auto-inout-in): Doc fixes.
+	(verilog-read-always-signals, verilog-auto-sense-sigs)
+	(verilog-auto-reset): Fix AUTORESET with always_comb and always_latch,
+	bug844.  Reported by Greg Hilton.
+
+2014-12-09  Alex Reed  <acreed4@gmail.com>  (tiny change)
+
+	* progmodes/verilog-mode.el (verilog-no-indent-begin-re):
+	Fix `verilog-indent-begin-after-if' nil not honoring 'forever',
+	'foreach', and 'do' keywords.
+	(verilog-endcomment-reason-re, verilog-beg-of-statement):
+	Fix labeling do-while blocks, bug842.
+	(verilog-backward-token): Fix indenting sensitivity lists with
+	named events, bug840.
+
 2014-12-09  Reto Zimmermann  <reto@gnu.org>
 
 	Sync with upstream vhdl mode v3.36.1.

lisp/progmodes/verilog-mode.el

@@ -123,7 +123,7 @@
 ;;; Code:
 
 ;; This variable will always hold the version number of the mode
-(defconst verilog-mode-version "2014-10-03-c075a49-vpo"
+(defconst verilog-mode-version "2014-11-12-aa4b777-vpo"
   "Version of this Verilog mode.")
 (defconst verilog-mode-release-emacs t
   "If non-nil, this version of Verilog mode was released with Emacs itself.")
@@ -2269,8 +2269,9 @@ find the errors."
 (defconst verilog-no-indent-begin-re
   (eval-when-compile
     (verilog-regexp-words
-     '( "if" "else" "while" "for" "repeat" "always" "always_comb" "always_ff" "always_latch"
+     '("always" "always_comb" "always_ff" "always_latch" "initial" "final" ;; procedural blocks
-	"initial" "final"))))
+       "if" "else"                                                         ;; conditional statements
+       "while" "for" "foreach" "repeat" "do" "forever" ))))                ;; loop statements
 
 (defconst verilog-ends-re
   ;; Parenthesis indicate type of keyword found
@@ -2328,6 +2329,7 @@ find the errors."
 		"endinterface"
 		"endpackage"
 		"endsequence"
+		"endproperty"
 		"endspecify"
 		"endtable"
 		"endtask"
@@ -2360,6 +2362,7 @@ find the errors."
           "\\(program\\)\\|"	   ; 13
           "\\(sequence\\)\\|"	   ; 14
 	  "\\(clocking\\)\\|"      ; 15
+	  "\\(property\\)\\|"      ; 16
 	  "\\)\\>\\)"))
 (defconst verilog-end-block-re
   (eval-when-compile
@@ -2424,7 +2427,7 @@ find the errors."
    "\\(\\<package\\>\\)\\|"
    "\\(\\<final\\>\\)\\|"
    "\\(@\\)\\|"
-   "\\(\\<while\\>\\)\\|"
+   "\\(\\<while\\>\\)\\|\\(\\<do\\>\\)\\|"
    "\\(\\<for\\(ever\\|each\\)?\\>\\)\\|"
    "\\(\\<repeat\\>\\)\\|\\(\\<wait\\>\\)\\|"
    "#"))
@@ -2518,15 +2521,20 @@ find the errors."
        "join" "join_any" "join_none"
        "end"
        "endcase"
-       "endconfig"
+       "endchecker"
        "endclass"
        "endclocking"
+       "endconfig"
        "endfunction"
        "endgenerate"
+       "endgroup"
        "endmodule"
        "endprimitive"
        "endinterface"
        "endpackage"
+       "endprogram"
+       "endproperty"
+       "endsequence"
        "endspecify"
        "endtable"
        "endtask" )
@@ -2756,10 +2764,45 @@ find the errors."
   "String used to mark end of excluded text.")
 (defconst verilog-preprocessor-re
   (eval-when-compile
+    (concat
+     ;; single words
+     "\\(?:"
      (verilog-regexp-words
-     `(
+      `("`__FILE__"
-       "`define" "`include" "`ifdef" "`ifndef" "`if" "`endif" "`else"
+	"`__LINE__"
-       ))))
+	"`celldefine"
+	"`else"
+	"`end_keywords"
+	"`endcelldefine"
+	"`endif"
+	"`nounconnected_drive"
+	"`resetall"
+	"`unconnected_drive"
+	"`undefineall"))
+     "\\)\\|\\(?:"
+     ;; two words: i.e. `ifdef DEFINE
+     "\\<\\(`elsif\\|`ifn?def\\|`undef\\|`default_nettype\\|`begin_keywords\\)\\>\\s-"
+     "\\)\\|\\(?:"
+     ;; `line number "filename" level
+     "\\<\\(`line\\)\\>\\s-+[0-9]+\\s-+\"[^\"]+\"\\s-+[012]"
+     "\\)\\|\\(?:"
+     ;;`include "file" or `include <file>
+     "\\<\\(`include\\)\\>\\s-+\\(?:\"[^\"]+\"\\|<[^>]+>\\)"
+     "\\)\\|\\(?:"
+     ;; `pragma <stuff> (no mention in IEEE 1800-2012 that pragma can span multiple lines
+     "\\<\\(`pragma\\)\\>\\s-+.+$"
+     "\\)\\|\\(?:"
+     ;; `timescale time_unit / time_precision
+     "\\<\\(`timescale\\)\\>\\s-+10\\{0,2\\}\\s-*[munpf]?s\\s-*\\/\\s-*10\\{0,2\\}\\s-*[munpf]?s"
+     "\\)\\|\\(?:"
+     ;; `define and `if can span multiple lines if line ends in '\'. NOTE: `if is not IEEE 1800-2012
+     ;; from http://www.emacswiki.org/emacs/MultilineRegexp
+     (concat "\\<\\(`define\\|`if\\)\\>" ;; directive
+	     "\\s-+" ;; separator
+	     "\\(.*\\(?:\n.*\\)*?\\)" ;; definition: to tend of line, the maybe more lines (excludes any trailing \n)
+	     "\\(?:\n\\s-*\n\\|\\'\\)") ;; blank line or EOF
+     "\\)"
+     )))
 
 (defconst verilog-keywords
   '( "`case" "`default" "`define" "`else" "`endfor" "`endif"
@@ -4126,9 +4169,7 @@ Uses `verilog-scan' cache."
     (while (and
 	    (> (marker-position e) (point))
 	    (verilog-re-search-forward
-	     (concat
+	     verilog-auto-end-comment-lines-re
-	      "\\<end\\(\\(function\\)\\|\\(task\\)\\|\\(module\\)\\|\\(primitive\\)\\|\\(interface\\)\\|\\(package\\)\\|\\(case\\)\\)?\\>"
-	      "\\|\\(`endif\\)\\|\\(`else\\)")
 	     nil 'move))
       (goto-char (match-beginning 0))
       (let ((indent-str (verilog-indent-line)))
@@ -4158,7 +4199,7 @@ Uses `verilog-scan' cache."
 	;; then move back a token and test again.
 	(not (or
 	      ;; stop if beginning of buffer
-	      (bolp)
+	      (bobp)
 	      ;; stop if we find a ;
 	      (= (preceding-char) ?\;)
 	      ;; stop if we see a named coverpoint
@@ -4189,13 +4230,15 @@ Uses `verilog-scan' cache."
 	      ;; stop if previous token is an ender
 	      (save-excursion
 		(verilog-backward-token)
-            (or
+		(looking-at verilog-end-block-re))))
-             (looking-at verilog-end-block-re)
-             (looking-at verilog-preprocessor-re))))) ;; end of test
       (verilog-backward-syntactic-ws)
       (verilog-backward-token))
     ;; Now point is where the previous line ended.
-    (verilog-forward-syntactic-ws)))
+    (verilog-forward-syntactic-ws)
+    ;; Skip forward over any preprocessor directives, as they have wacky indentation
+    (if (looking-at verilog-preprocessor-re)
+	(progn (goto-char (match-end 0))
+	       (verilog-forward-syntactic-ws)))))
 
 (defun verilog-beg-of-statement-1 ()
   "Move backward to beginning of statement."
@@ -4209,13 +4252,12 @@ Uses `verilog-scan' cache."
         (verilog-backward-syntactic-ws)
         (if (or (bolp)
                 (= (preceding-char) ?\;)
-		(save-excursion
+		(progn
 		  (verilog-backward-token)
 		  (looking-at verilog-ends-re)))
             (progn
               (goto-char pt)
-              (throw 'done t))
+              (throw 'done t)))))
-          (verilog-backward-token))))
     (verilog-forward-syntactic-ws)))
 ;
 ;    (while (and
@@ -4773,10 +4815,10 @@ primitive or interface named NAME."
 		  (cond
 		   ((match-end 5) ;; of verilog-end-block-ordered-re
 		    (setq reg "\\(\\<function\\>\\)\\|\\(\\<\\(endfunction\\|task\\|\\(macro\\)?module\\|primitive\\)\\>\\)")
-		    (setq name-re "\\w+\\s-*("))
+		    (setq name-re "\\w+\\(?:\n\\|\\s-\\)*[(;]"))
 		   ((match-end 6) ;; of verilog-end-block-ordered-re
 		    (setq reg "\\(\\<task\\>\\)\\|\\(\\<\\(endtask\\|function\\|\\(macro\\)?module\\|primitive\\)\\>\\)")
-		    (setq name-re "\\w+\\s-*("))
+		    (setq name-re "\\w+\\(?:\n\\|\\s-\\)*[(;]"))
 		   ((match-end 7) ;; of verilog-end-block-ordered-re
 		    (setq reg "\\(\\<\\(macro\\)?module\\>\\)\\|\\<endmodule\\>"))
 		   ((match-end 8) ;; of verilog-end-block-ordered-re
@@ -4795,6 +4837,8 @@ primitive or interface named NAME."
 		    (setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<\\(endsequence\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
 		   ((match-end 15) ;; of verilog-end-block-ordered-re
 		    (setq reg "\\(\\<clocking\\>\\)\\|\\<endclocking\\>"))
+		   ((match-end 16) ;; of verilog-end-block-ordered-re
+		    (setq reg "\\(\\<property\\>\\)\\|\\<endproperty\\>"))
 
 		   (t (error "Problem in verilog-set-auto-endcomments")))
 		  (let (b e)
@@ -5849,7 +5893,9 @@ Set point to where line starts."
    (;-- any of begin|initial|while are complete statements; 'begin : foo' is also complete
     t
     (forward-word -1)
-    (while (= (preceding-char) ?\_)
+    (while (or (= (preceding-char) ?\_)
+               (= (preceding-char) ?\@)
+               (= (preceding-char) ?\.))
       (forward-word -1))
     (cond
      ((looking-at "\\<else\\>")
@@ -6103,14 +6149,18 @@ Return >0 for nested struct."
 (defun verilog-at-constraint-p ()
   "If at the { of a constraint or coverpoint definition, return true, moving point to constraint."
   (if (save-excursion
+	(let ((p (point)))
 	(and
 	 (equal (char-after) ?\{)
 	 (forward-list)
 	 (progn (backward-char 1)
 		(verilog-backward-ws&directives)
+	  (and
 		(or (equal (char-before) ?\{) ;; empty case
                     (equal (char-before) ?\;)
-                    (equal (char-before) ?\})))))
+                    (equal (char-before) ?\}))
+                    ;; skip what looks like bus repitition operator {#{
+                    (not (string-match "^{\\s-*[0-9]+\\s-*{" (buffer-substring p (point)))))))))
       (progn
         (let ( (pt (point)) (pass 0))
           (verilog-backward-ws&directives)
@@ -6429,6 +6479,9 @@ Only look at a few lines to determine indent level."
 	   (looking-at verilog-declaration-re))
       (verilog-indent-declaration ind))
 
+     (;-- form feeds - ignored as bug in indent-line-to in < 24.5
+      (looking-at "\f"))
+
      (;-- Everything else
       t
       (let ((val (eval (cdr (assoc type verilog-indent-alist)))))
@@ -8894,7 +8947,6 @@ IGNORE-NEXT is true to ignore next token, fake from inside case statement."
   (save-excursion
     (let* (;;(dbg "")
 	   sigs-out-d sigs-out-i sigs-out-unk sigs-temp sigs-in)
-      (search-forward ")")
       (verilog-read-always-signals-recurse nil nil nil)
       (setq sigs-out-i (append sigs-out-i sigs-out-unk)
 	    sigs-out-unk nil)
@@ -11731,6 +11783,9 @@ Limitations:
 
   Typedefs must match `verilog-typedef-regexp', which is disabled by default.
 
+  Types are added to declarations if an AUTOLOGIC or
+  `verilog-auto-wire-type' is set to logic.
+
   Signals matching `verilog-auto-output-ignore-regexp' are not included.
 
 An example (see `verilog-auto-inst' for what else is going on here):
@@ -11872,6 +11927,9 @@ Limitations:
 
   Typedefs must match `verilog-typedef-regexp', which is disabled by default.
 
+  Types are added to declarations if an AUTOLOGIC or
+  `verilog-auto-wire-type' is set to logic.
+
   Signals matching `verilog-auto-input-ignore-regexp' are not included.
 
 An example (see `verilog-auto-inst' for what else is going on here):
@@ -11952,6 +12010,9 @@ Limitations:
 
   Typedefs must match `verilog-typedef-regexp', which is disabled by default.
 
+  Types are added to declarations if an AUTOLOGIC or
+  `verilog-auto-wire-type' is set to logic.
+
   Signals matching `verilog-auto-inout-ignore-regexp' are not included.
 
 An example (see `verilog-auto-inst' for what else is going on here):
@@ -12068,13 +12129,14 @@ same expansion will result from only extracting signals starting with i:
 
 	   /*AUTOINOUTMODULE(\"ExampMain\",\"^i\")*/
 
-You may also provide an optional second regular expression, in
+You may also provide an optional third argument regular
-which case only signals which have that pin direction and data
+expression, in which case only signals which have that pin
-type will be included.  This matches against everything before
+direction and data type matching that regular expression will be
-the signal name in the declaration, for example against
+included.  This matches against everything before the signal name
-\"input\" (single bit), \"output logic\" (direction and type) or
+in the declaration, for example against \"input\" (single bit),
-\"output [1:0]\" (direction and implicit type).  You also
+\"output logic\" (direction and type) or \"output
-probably want to skip spaces in your regexp.
+[1:0]\" (direction and implicit type).  You also probably want to
+skip spaces in your regexp.
 
 For example, the below will result in matching the output \"o\"
 against the previous example's module:
@@ -12193,7 +12255,21 @@ You may also provide an optional regular expression, in which case only
 signals matching the regular expression will be included.  For example the
 same expansion will result from only extracting signals starting with i:
 
-	   /*AUTOINOUTCOMP(\"ExampMain\",\"^i\")*/"
+	   /*AUTOINOUTCOMP(\"ExampMain\",\"^i\")*/
+
+You may also provide an optional third argument regular
+expression, in which case only signals which have that pin
+direction and data type matching that regular expression will be
+included.  This matches against everything before the signal name
+in the declaration, for example against \"input\" (single bit),
+\"output logic\" (direction and type) or \"output
+[1:0]\" (direction and implicit type).  You also probably want to
+skip spaces in your regexp.
+
+For example, the below will result in matching the output \"o\"
+against the previous example's module:
+
+	   /*AUTOINOUTCOMP(\"ExampMain\",\"\",\"^output.*\")*/"
   (verilog-auto-inout-module t nil))
 
 (defun verilog-auto-inout-in ()
@@ -12244,7 +12320,7 @@ You may also provide an optional regular expression, in which case only
 signals matching the regular expression will be included.  For example the
 same expansion will result from only extracting signals starting with i:
 
-	   /*AUTOINOUTCOMP(\"ExampMain\",\"^i\")*/"
+	   /*AUTOINOUTIN(\"ExampMain\",\"^i\")*/"
   (verilog-auto-inout-module nil t))
 
 (defun verilog-auto-inout-param ()
@@ -12516,7 +12592,9 @@ See `verilog-auto-insert-lisp' for examples."
 
 (defun verilog-auto-sense-sigs (moddecls presense-sigs)
   "Return list of signals for current AUTOSENSE block."
-  (let* ((sigss (verilog-read-always-signals))
+  (let* ((sigss (save-excursion
+		  (search-forward ")")
+		  (verilog-read-always-signals)))
 	 (sig-list (verilog-signals-not-params
 		    (verilog-signals-not-in (verilog-alw-get-inputs sigss)
 					    (append (and (not verilog-auto-sense-include-inputs)
@@ -12706,11 +12784,12 @@ Typing \\[verilog-auto] will make this into:
 			   (save-excursion
 			     (verilog-read-signals
 			      (save-excursion
-				(verilog-re-search-backward-quick "\\(@\\|\\<begin\\>\\|\\<if\\>\\|\\<case\\>\\)" nil t)
+				(verilog-re-search-backward-quick
+				 "\\(@\\|\\<\\(begin\\|if\\|case\\|always\\(_latch\\|_ff\\|_comb\\)?\\)\\>\\)" nil t)
 				(point))
 			      (point)))))
       (save-excursion
-	(verilog-re-search-backward-quick "@" nil t)
+	(verilog-re-search-backward-quick "\\(@\\|\\<\\(always\\(_latch\\|_ff\\|_comb\\)?\\)\\>\\)" nil t)
         (setq sigss (verilog-read-always-signals)))
       (setq dly-list (verilog-alw-get-outputs-delayed sigss))
       (setq sig-list (verilog-signals-not-in (append