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Remove otiose "this document describes the".
Add "anyone porting the MPS to a new platform" to the readership of design documents that they might need to consult. Copied from Perforce Change: 187377 ServerID: perforce.ravenbrook.com
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@ -17,10 +17,9 @@ Virtual Memory Arena
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Introduction
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------------
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_`.intro`: This document describes the detailed design of the Virtual
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Memory Arena Class of the Memory Pool System. The VM Arena Class is
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just one class available in the MPS. The generic arena part is
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described in design.mps.arena_.
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_`.intro`: This is the design of the Virtual Memory Arena Class of the
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Memory Pool System. The VM Arena Class is just one class available in
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the MPS. The generic arena part is described in design.mps.arena_.
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.. _design.mps.arena: arena
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@ -15,8 +15,8 @@ Allocation buffers and allocation points
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Introduction
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------------
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_`.scope`: This document describes the design of allocation buffers
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and allocation points.
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_`.scope`: This is the design of allocation buffers and allocation
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points.
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_`.purpose`: The purpose of this document is to record design
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decisions made concerning allocation buffers and allocation points and
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@ -20,6 +20,9 @@ _`.intro`: This document describes how the `Memory Pool System
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that it can target different architectures, operating systems, build
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environments, varieties, and products.
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_`.readership`: Any MPS developer; anyone porting the MPS to a new
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platform.
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Requirements
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@ -15,8 +15,7 @@ Free list allocator
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Introduction
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------------
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_`.intro`: This document describes the free list allocator for the
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Memory Pool System.
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_`.intro`: This is the design of the free list allocator.
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_`.readership`: Any MPS developer.
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@ -15,10 +15,10 @@ Lock module
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Introduction
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------------
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_`.intro`: This document describes the design of the lock module in
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the Memory Pool System.
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_`.intro`: This is the design of the lock module.
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_`.readership`: Any MPS developer.
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_`.readership`: Any MPS developer; anyone porting the MPS to a new
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platform.
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Background
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@ -15,8 +15,7 @@ Nailboards for ambiguously referenced segments
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Introduction
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------------
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_`.intro`: This document describes the nailboard design for the Memory
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Pool System.
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_`.intro`: This is the design of the nailboard module.
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_`.readership`: Any MPS developer.
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@ -36,11 +36,10 @@ req.mps that captures the commonalities between the products -- pekka
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Overview
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--------
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_`.overview`: This document describes the design of the AMS (Automatic
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Mark-and-Sweep) pool class. The AMS pool is a proof-of-concept design
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for a mark-sweep pool in the MPS. It's not meant to be efficient, but
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it could serve as a model for an implementation of a more advanced
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pool (such as EPVM).
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_`.overview`: This is the design of the AMS (Automatic Mark-and-Sweep)
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pool class. The AMS pool is a proof-of-concept design for a mark-sweep
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pool in the MPS. It's not meant to be efficient, but it could serve as
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a model for an implementation of a more advanced pool (such as EPVM).
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Requirements
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@ -18,7 +18,8 @@ Introduction
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_`.intro`: This is the design of the protection mutator context
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module.
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_`.readership`: Any MPS developer.
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_`.readership`: Any MPS developer; anyone porting the MPS to a new
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platform.
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_`.overview`: The protection mutator context module decodes the
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*context* of a mutator thread at the point when it caused a protection
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@ -15,10 +15,10 @@ Memory protection
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Introduction
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------------
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_`.intro`: This document describes the design of the memory protection
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module.
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_`.intro`: This is the design of the memory protection module.
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_`.readership`: Any MPS developer.
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_`.readership`: Any MPS developer; anyone porting the MPS to a new
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platform.
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_`.overview`: The memory protection module ensures that the mutator
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sees a consistent view of memory during incremental collection, by
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@ -15,7 +15,7 @@ Segment data structure
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Introduction
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------------
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_`.intro`: This document describes the MPS Segment data structure.
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_`.intro`: This is the design of the segment data structure.
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Overview
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@ -15,10 +15,10 @@ Stack probe
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Introduction
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------------
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_`.intro`: This document describes the design of the stack probe
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module.
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_`.intro`: This is the design of the stack probe module.
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_`.readership`: Any MPS developer.
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_`.readership`: Any MPS developer; anyone porting the MPS to a new
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platform.
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_`.overview`: This module ensures that the stack cannot overflow while
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the MPS is holding a lock.
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@ -15,10 +15,11 @@ Stack and register scanning
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Introduction
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------------
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_`.intro`: This document describes the design of the stack and
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register scanning module.
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_`.intro`: This is the design of the stack and register scanning
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module.
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_`.readership`: Any MPS developer.
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_`.readership`: Any MPS developer; anyone porting the MPS to a new
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platform.
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_`.overview`: This module locates and scans references in the control
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stack and registers of the *current* thread.
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@ -15,8 +15,8 @@ Multi-threaded testing
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Introduction
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------------
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_`.intro`: This document describes the design for multi-threaded
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testing in the Memory Pool System.
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_`.intro`: This is the design of the multi-threaded testing module
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in the Memory Pool System.
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_`.readership`: Any MPS developer.
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@ -17,7 +17,8 @@ Introduction
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_`.intro`: This is the design of the thread manager module.
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_`.readership`: Any MPS developer.
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_`.readership`: Any MPS developer; anyone porting the MPS to a new
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platform.
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_`.overview`: The thread manager implements two features that allow
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the MPS to work in a multi-threaded environment: exclusive access to
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@ -15,10 +15,10 @@ Virtual mapping
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Introduction
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------------
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_`.intro`: This document describes the design of the virtual mapping
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module.
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_`.intro`: This is the design of the virtual mapping module.
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_`.readership`: Any MPS developer.
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_`.readership`: Any MPS developer; anyone porting the MPS to a new
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platform.
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_`.overview`: The virtual mapping module provides a simple, portable,
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low-level interface to address space, with functions for reserving,
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