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(verilog-type-font-keywords): Add leda and 0in
as pragma keywords. (verilog-pretty-expr): Support lining up assignments which include part selects. (verilog-mode): More portable check for the availability of hideshow support. (verilog-do-indent): Remove special indent for declarations inside a parenthetical list. The code is ill-advised, and doesn't work given the new user defined types. (verilog-set-auto-endcomments): Enhance function automatic endcomment to support functions that return user defined types. (verilog-mode): Add code to tell which-function-mode minor mode that Verilog supports this feature.
This commit is contained in:
Dan Nicolaescu
parent
231b351dcc
commit
9c059794a2
2 changed files with 83 additions and 64 deletions
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@ -118,9 +118,9 @@
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;;; Code:
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;; This variable will always hold the version number of the mode
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(defconst verilog-mode-version "404"
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(defconst verilog-mode-version "423"
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"Version of this Verilog mode.")
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(defconst verilog-mode-release-date "2008-03-02-GNU"
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(defconst verilog-mode-release-date "2008-05-07-GNU"
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"Release date of this Verilog mode.")
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(defconst verilog-mode-release-emacs t
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"If non-nil, this version of Verilog mode was released with Emacs itself.")
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@ -1953,7 +1953,7 @@ See also `verilog-font-lock-extra-types'.")
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(verilog-pragma-keywords
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(eval-when-compile
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(verilog-regexp-opt
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'("surefire" "synopsys" "rtl_synthesis" "verilint" ) nil
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'("surefire" "synopsys" "rtl_synthesis" "verilint" "leda" "0in") nil
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)))
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(verilog-p1800-keywords
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@ -2514,12 +2514,16 @@ Key bindings specific to `verilog-mode-map' are:
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;; Tell imenu how to handle Verilog.
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(make-local-variable 'imenu-generic-expression)
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(setq imenu-generic-expression verilog-imenu-generic-expression)
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;; Tell which-func-modes that imenu knows about verilog
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(when (boundp 'which-function-modes)
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(add-to-list 'which-func-modes 'verilog-mode))
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;; hideshow support
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(unless (assq 'verilog-mode hs-special-modes-alist)
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(setq hs-special-modes-alist
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(cons '(verilog-mode-mode "\\<begin\\>" "\\<end\\>" nil
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verilog-forward-sexp-function)
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hs-special-modes-alist)))
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(when (boundp 'hs-special-modes-alist)
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(unless (assq 'verilog-mode hs-special-modes-alist)
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(setq hs-special-modes-alist
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(cons '(verilog-mode-mode "\\<begin\\>" "\\<end\\>" nil
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verilog-forward-sexp-function)
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hs-special-modes-alist))))
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;; Stuff for autos
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(add-hook 'write-contents-hooks 'verilog-auto-save-check) ; already local
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@ -3468,7 +3472,7 @@ primitive or interface named NAME."
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(;- this is end{function,generate,task,module,primitive,table,generate}
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;- which can not be nested.
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t
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(let (string reg (width nil))
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(let (string reg (name-re nil))
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(end-of-line)
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(if kill-existing-comment
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(save-match-data
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@ -3478,7 +3482,8 @@ primitive or interface named NAME."
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(cond
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((match-end 5) ;; of verilog-end-block-ordered-re
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(setq reg "\\(\\<function\\>\\)\\|\\(\\<\\(endfunction\\|task\\|\\(macro\\)?module\\|primitive\\)\\>\\)")
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(setq width "\\(\\s-*\\(\\[[^]]*\\]\\)\\|\\(real\\(time\\)?\\)\\|\\(integer\\)\\|\\(time\\)\\)?"))
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(setq name-re "\\w+\\s-*(")
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)
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((match-end 6) ;; of verilog-end-block-ordered-re
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(setq reg "\\(\\<task\\>\\)\\|\\(\\<\\(endtask\\|function\\|\\(macro\\)?module\\|primitive\\)\\>\\)"))
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((match-end 7) ;; of verilog-end-block-ordered-re
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@ -3509,9 +3514,9 @@ primitive or interface named NAME."
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(setq b (progn
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(skip-chars-forward "^ \t")
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(verilog-forward-ws&directives)
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(if (and width (looking-at width))
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(if (and name-re (verilog-re-search-forward name-re nil 'move))
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(progn
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(goto-char (match-end 0))
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(goto-char (match-beginning 0))
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(verilog-forward-ws&directives)))
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(point))
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e (progn
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@ -4683,10 +4688,8 @@ Only look at a few lines to determine indent level."
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(skip-chars-forward " \t")
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(current-column))))
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(indent-line-to val)
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(if (and (not (verilog-in-struct-region-p))
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(looking-at verilog-declaration-re))
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(verilog-indent-declaration ind))))
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))
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(;-- Handle the ends
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(or
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(looking-at verilog-end-block-re )
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@ -4920,7 +4923,7 @@ ARG is ignored, for `comment-indent-function' compatibility."
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(if (or (eq myre nil)
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(string-equal myre ""))
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(setq myre "\\(<\\|:\\)?="))
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(setq myre (concat "\\(^[^;#:<=>]*\\)\\(" myre "\\)"))
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(setq myre (concat "\\(^[^;#<=>]*\\)\\(" myre "\\)"))
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(let ((rexp(concat "^\\s-*" verilog-complete-reg)))
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(beginning-of-line)
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(if (and (not (looking-at rexp ))
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@ -7372,12 +7375,12 @@ Cache the output of function so next call may have faster access."
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func-returns)
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(setq func-returns (funcall function))
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(when fontlocked (font-lock-mode t))
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;; Cache for next time
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(setq verilog-modi-cache-list
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;; Cache for next time
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(setq verilog-modi-cache-list
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(cons (list (list modi function)
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(buffer-modified-tick)
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(visited-file-modtime)
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func-returns)
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(buffer-modified-tick)
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(visited-file-modtime)
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func-returns)
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verilog-modi-cache-list))
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func-returns))))))
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@ -7842,10 +7845,10 @@ Typing \\[verilog-inject-auto] will make this into:
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(goto-char (point-min))
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(while (verilog-re-search-forward-quick "\\<always\\s *@\\s *(" nil t)
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(let* ((start-pt (point))
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(modi (verilog-modi-current))
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(modi (verilog-modi-current))
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(moddecls (verilog-modi-get-decls modi))
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pre-sigs
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got-sigs)
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pre-sigs
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got-sigs)
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(backward-char 1)
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(forward-sexp 1)
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(backward-char 1) ;; End )
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@ -8007,7 +8010,7 @@ Avoid declaring ports manually, as it makes code harder to maintain."
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(save-excursion
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(let* ((modi (verilog-modi-current))
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(moddecls (verilog-modi-get-decls modi))
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(skip-pins (aref (verilog-read-arg-pins) 0)))
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(skip-pins (aref (verilog-read-arg-pins) 0)))
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(verilog-repair-open-comma)
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(verilog-auto-arg-ports (verilog-signals-not-in
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(verilog-decls-get-outputs moddecls)
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@ -9743,55 +9746,55 @@ Wilson Snyder (wsnyder@wsnyder.org), and/or see http://www.veripool.com."
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(verilog-getopt-flags)
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;; From here on out, we can cache anything we read from disk
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(verilog-preserve-dir-cache
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;; These two may seem obvious to do always, but on large includes it can be way too slow
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(when verilog-auto-read-includes
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(verilog-read-includes)
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(verilog-read-defines nil nil t))
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;; This particular ordering is important
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;; INST: Lower modules correct, no internal dependencies, FIRST
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;; These two may seem obvious to do always, but on large includes it can be way too slow
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(when verilog-auto-read-includes
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(verilog-read-includes)
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(verilog-read-defines nil nil t))
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;; This particular ordering is important
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;; INST: Lower modules correct, no internal dependencies, FIRST
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(verilog-preserve-modi-cache
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;; Clear existing autos else we'll be screwed by existing ones
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(verilog-delete-auto)
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;; Injection if appropriate
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(when inject
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(verilog-inject-inst)
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(verilog-inject-sense)
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(verilog-inject-arg))
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;;
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;; Clear existing autos else we'll be screwed by existing ones
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(verilog-delete-auto)
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;; Injection if appropriate
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(when inject
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(verilog-inject-inst)
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(verilog-inject-sense)
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(verilog-inject-arg))
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;;
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(verilog-auto-re-search-do "/\\*AUTOINSTPARAM\\*/" 'verilog-auto-inst-param)
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(verilog-auto-re-search-do "/\\*AUTOINST\\*/" 'verilog-auto-inst)
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(verilog-auto-re-search-do "\\.\\*" 'verilog-auto-star)
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;; Doesn't matter when done, but combine it with a common changer
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(verilog-auto-re-search-do "/\\*\\(AUTOSENSE\\|AS\\)\\*/" 'verilog-auto-sense)
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(verilog-auto-re-search-do "/\\*AUTORESET\\*/" 'verilog-auto-reset)
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;; Must be done before autoin/out as creates a reg
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(verilog-auto-re-search-do "/\\*AUTOASCIIENUM([^)]*)\\*/" 'verilog-auto-ascii-enum)
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;;
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;; first in/outs from other files
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(verilog-auto-re-search-do "/\\*AUTOINOUTMODULE([^)]*)\\*/" 'verilog-auto-inout-module)
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;; next in/outs which need previous sucked inputs first
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(verilog-auto-re-search-do "/\\*AUTOOUTPUT\\((\"[^\"]*\")\\)\\*/"
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'(lambda () (verilog-auto-output t)))
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(verilog-auto-re-search-do "/\\*AUTOOUTPUT\\*/" 'verilog-auto-output)
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(verilog-auto-re-search-do "/\\*AUTOINPUT\\((\"[^\"]*\")\\)\\*/"
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'(lambda () (verilog-auto-input t)))
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(verilog-auto-re-search-do "/\\*AUTOINPUT\\*/" 'verilog-auto-input)
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(verilog-auto-re-search-do "/\\*AUTOINOUT\\((\"[^\"]*\")\\)\\*/"
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'(lambda () (verilog-auto-inout t)))
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(verilog-auto-re-search-do "/\\*AUTOINOUT\\*/" 'verilog-auto-inout)
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;; Then tie off those in/outs
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;; Doesn't matter when done, but combine it with a common changer
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(verilog-auto-re-search-do "/\\*\\(AUTOSENSE\\|AS\\)\\*/" 'verilog-auto-sense)
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(verilog-auto-re-search-do "/\\*AUTORESET\\*/" 'verilog-auto-reset)
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;; Must be done before autoin/out as creates a reg
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(verilog-auto-re-search-do "/\\*AUTOASCIIENUM([^)]*)\\*/" 'verilog-auto-ascii-enum)
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;;
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;; first in/outs from other files
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(verilog-auto-re-search-do "/\\*AUTOINOUTMODULE([^)]*)\\*/" 'verilog-auto-inout-module)
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;; next in/outs which need previous sucked inputs first
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(verilog-auto-re-search-do "/\\*AUTOOUTPUT\\((\"[^\"]*\")\\)\\*/"
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'(lambda () (verilog-auto-output t)))
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(verilog-auto-re-search-do "/\\*AUTOOUTPUT\\*/" 'verilog-auto-output)
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(verilog-auto-re-search-do "/\\*AUTOINPUT\\((\"[^\"]*\")\\)\\*/"
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'(lambda () (verilog-auto-input t)))
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(verilog-auto-re-search-do "/\\*AUTOINPUT\\*/" 'verilog-auto-input)
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(verilog-auto-re-search-do "/\\*AUTOINOUT\\((\"[^\"]*\")\\)\\*/"
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'(lambda () (verilog-auto-inout t)))
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(verilog-auto-re-search-do "/\\*AUTOINOUT\\*/" 'verilog-auto-inout)
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;; Then tie off those in/outs
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(verilog-auto-re-search-do "/\\*AUTOTIEOFF\\*/" 'verilog-auto-tieoff)
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;; Wires/regs must be after inputs/outputs
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;; Wires/regs must be after inputs/outputs
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(verilog-auto-re-search-do "/\\*AUTOWIRE\\*/" 'verilog-auto-wire)
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(verilog-auto-re-search-do "/\\*AUTOREG\\*/" 'verilog-auto-reg)
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(verilog-auto-re-search-do "/\\*AUTOREGINPUT\\*/" 'verilog-auto-reg-input)
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;; outputevery needs AUTOOUTPUTs done first
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;; outputevery needs AUTOOUTPUTs done first
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(verilog-auto-re-search-do "/\\*AUTOOUTPUTEVERY\\*/" 'verilog-auto-output-every)
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;; After we've created all new variables
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;; After we've created all new variables
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(verilog-auto-re-search-do "/\\*AUTOUNUSED\\*/" 'verilog-auto-unused)
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;; Must be after all inputs outputs are generated
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;; Must be after all inputs outputs are generated
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(verilog-auto-re-search-do "/\\*AUTOARG\\*/" 'verilog-auto-arg)
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;; Fix line numbers (comments only)
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;; Fix line numbers (comments only)
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(verilog-auto-templated-rel)))
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;;
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(run-hooks 'verilog-auto-hook)
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