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Reference the design.

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 Change: 194657
This commit is contained in:
Gareth Rees 2018-07-15 20:41:07 +01:00
parent 817f014bd3
commit 72001fd9d2
1 changed files with 3 additions and 4 deletions
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7
mps/code/seg.c
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@ -1,7 +1,7 @@
/* seg.c: SEGMENTS
*
* $Id$
* Copyright (c) 2001-2016 Ravenbrook Limited. See end of file for license.
* Copyright (c) 2001-2018 Ravenbrook Limited. See end of file for license.
*
* .design: The design for this module is <design/seg/>.
*
@ -860,8 +860,7 @@ Bool SegCheck(Seg seg)
CHECKL(AddrIsArenaGrain(TractBase(seg->firstTract), arena));
CHECKL(AddrIsArenaGrain(seg->limit, arena));
CHECKL(seg->limit > TractBase(seg->firstTract));
/* Can't BoolCheck seg->queued because compilers warn about that on
single-bit fields. */
/* CHECKL(BoolCheck(seq->queued)); <design/type/#bool.bitfield.check> */
/* Each tract of the segment must agree about the segment and its
* pool. Note that even if the CHECKs are compiled away there is
@ -2165,7 +2164,7 @@ void SegClassMixInNoSplitMerge(SegClass klass)
/* C. COPYRIGHT AND LICENSE
*
* Copyright (C) 2001-2016 Ravenbrook Limited <http://www.ravenbrook.com/>.
* Copyright (C) 2001-2018 Ravenbrook Limited <http://www.ravenbrook.com/>.
* All rights reserved. This is an open source license. Contact
* Ravenbrook for commercial licensing options.
*