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(verilog-easy-menu-filter): New function.
(verilog-stmt-menu, verilog-menu): Add :help and filter it. (verilog-customize, verilog-font-customize) (electric-verilog-backward-sexp, electric-verilog-forward-sexp) (verilog-mode): Update documentation strings to match tool tips. (verilog-auto-search-do, verilog-auto-re-search-do) (verilog-skip-forward-comment-or-string): Fix verilog-auto expansion when a .* appears inside a string. (verilog-re-search-forward, verilog-re-search-backward): Add comment to recall how this works.
This commit is contained in:
Dan Nicolaescu
parent
7d17537fac
commit
495ab0d547
2 changed files with 266 additions and 154 deletions
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@ -257,13 +257,35 @@ STRING should be given if the last search was by `string-match' on STRING."
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"Call 'regexp-opt' with word delimiters for the words A."
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(concat "\\<" (verilog-regexp-opt a t) "\\>")))
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(defun verilog-easy-menu-filter (menu)
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"Filter a easy-menu-define to support new features."
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(cond ((not (featurep 'xemacs))
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menu) ;; GNU Emacs - passthru
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;; Xemacs doesn't support :help. Strip it.
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;; Recursively filter the a submenu
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((listp menu)
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(mapcar 'verilog-easy-menu-filter menu))
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;; Look for [:help "blah"] and remove
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((vectorp menu)
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(let ((i 0) (out []))
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(while (< i (length menu))
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(if (equal `:help (aref menu i))
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(setq i (+ 2 i))
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(setq out (vconcat out (vector (aref menu i)))
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i (1+ i))))
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out))
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(t menu))) ;; Default - ok
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;;(verilog-easy-menu-filter
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;; `("Verilog" ("MA" ["SAA" nil :help "Help SAA"] ["SAB" nil :help "Help SAA"])
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;; "----" ["MB" nil :help "Help MB"]))
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(defun verilog-customize ()
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"Link to customize screen for Verilog."
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"Customize variables and other settings used by Verilog-Mode."
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(interactive)
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(customize-group 'verilog-mode))
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(defun verilog-font-customize ()
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"Link to customize fonts used for Verilog."
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"Customize fonts used by Verilog-Mode."
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(interactive)
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(if (fboundp 'customize-apropos)
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(customize-apropos "font-lock-*" 'faces)))
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@ -966,137 +988,221 @@ If set will become buffer local.")
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;; menus
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(easy-menu-define
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verilog-menu verilog-mode-map "Menu for Verilog mode"
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`("Verilog"
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("Choose Compilation Action"
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["None"
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(progn
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(setq verilog-tool nil)
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(verilog-set-compile-command))
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:style radio
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:selected (equal verilog-tool nil)]
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["Lint"
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(progn
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(setq verilog-tool 'verilog-linter)
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(verilog-set-compile-command))
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:style radio
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:selected (equal verilog-tool `verilog-linter)]
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["Coverage"
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(progn
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(setq verilog-tool 'verilog-coverage)
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(verilog-set-compile-command))
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:style radio
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:selected (equal verilog-tool `verilog-coverage)]
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["Simulator"
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(progn
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(setq verilog-tool 'verilog-simulator)
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(verilog-set-compile-command))
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:style radio
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:selected (equal verilog-tool `verilog-simulator)]
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["Compiler"
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(progn
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(setq verilog-tool 'verilog-compiler)
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(verilog-set-compile-command))
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:style radio
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:selected (equal verilog-tool `verilog-compiler)]
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)
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("Move"
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["Beginning of function" verilog-beg-of-defun
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:keys "C-M-a"]
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["End of function" verilog-end-of-defun
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:keys "C-M-e"]
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["Mark function" verilog-mark-defun
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:keys "C-M-h"]
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["Goto function/module" verilog-goto-defun t]
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["Move to beginning of block" electric-verilog-backward-sexp t]
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["Move to end of block" electric-verilog-forward-sexp t]
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)
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("Comments"
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["Comment Region" verilog-comment-region t]
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["UnComment Region" verilog-uncomment-region t]
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["Multi-line comment insert" verilog-star-comment t]
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["Lint error to comment" verilog-lint-off t]
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)
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"----"
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["Compile" compile t]
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["AUTO, Save, Compile" verilog-auto-save-compile t]
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["Next Compile Error" next-error t]
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["Ignore Lint Warning at point" verilog-lint-off t]
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"----"
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["Line up declarations around point" verilog-pretty-declarations t]
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["Line up equations around point" verilog-pretty-expr t]
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["Redo/insert comments on every end" verilog-label-be t]
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["Expand [x:y] vector line" verilog-expand-vector t]
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["Insert begin-end block" verilog-insert-block t]
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["Complete word" verilog-complete-word t]
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"----"
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["Recompute AUTOs" verilog-auto t]
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["Kill AUTOs" verilog-delete-auto t]
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["Inject AUTOs" verilog-inject-auto t]
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("AUTO Help..."
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["AUTO General" (describe-function 'verilog-auto) t]
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["AUTO Library Flags" (describe-variable 'verilog-library-flags) t]
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["AUTO Library Path" (describe-variable 'verilog-library-directories) t]
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["AUTO Library Files" (describe-variable 'verilog-library-files) t]
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["AUTO Library Extensions" (describe-variable 'verilog-library-extensions) t]
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["AUTO `define Reading" (describe-function 'verilog-read-defines) t]
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["AUTO `include Reading" (describe-function 'verilog-read-includes) t]
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["AUTOARG" (describe-function 'verilog-auto-arg) t]
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["AUTOASCIIENUM" (describe-function 'verilog-auto-ascii-enum) t]
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["AUTOINOUTMODULE" (describe-function 'verilog-auto-inout-module) t]
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["AUTOINOUT" (describe-function 'verilog-auto-inout) t]
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["AUTOINPUT" (describe-function 'verilog-auto-input) t]
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["AUTOINST" (describe-function 'verilog-auto-inst) t]
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["AUTOINST (.*)" (describe-function 'verilog-auto-star) t]
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["AUTOINSTPARAM" (describe-function 'verilog-auto-inst-param) t]
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["AUTOOUTPUT" (describe-function 'verilog-auto-output) t]
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["AUTOOUTPUTEVERY" (describe-function 'verilog-auto-output-every) t]
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["AUTOREG" (describe-function 'verilog-auto-reg) t]
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["AUTOREGINPUT" (describe-function 'verilog-auto-reg-input) t]
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["AUTORESET" (describe-function 'verilog-auto-reset) t]
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["AUTOSENSE" (describe-function 'verilog-auto-sense) t]
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["AUTOTIEOFF" (describe-function 'verilog-auto-tieoff) t]
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["AUTOUNUSED" (describe-function 'verilog-auto-unused) t]
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["AUTOWIRE" (describe-function 'verilog-auto-wire) t]
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)
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"----"
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["Submit bug report" verilog-submit-bug-report t]
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["Version and FAQ" verilog-faq t]
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["Customize Verilog Mode..." verilog-customize t]
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["Customize Verilog Fonts & Colors" verilog-font-customize t]))
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(verilog-easy-menu-filter
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'("Verilog"
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("Choose Compilation Action"
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["None"
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(progn
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(setq verilog-tool nil)
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(verilog-set-compile-command))
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:style radio
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:selected (equal verilog-tool nil)
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:help "When invoking compilation, use compile-command"]
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["Lint"
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(progn
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(setq verilog-tool 'verilog-linter)
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(verilog-set-compile-command))
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:style radio
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:selected (equal verilog-tool `verilog-linter)
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:help "When invoking compilation, use lint checker"]
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["Coverage"
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(progn
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(setq verilog-tool 'verilog-coverage)
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(verilog-set-compile-command))
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:style radio
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:selected (equal verilog-tool `verilog-coverage)
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:help "When invoking compilation, annotate for coverage"]
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["Simulator"
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(progn
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(setq verilog-tool 'verilog-simulator)
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(verilog-set-compile-command))
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:style radio
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:selected (equal verilog-tool `verilog-simulator)
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:help "When invoking compilation, interpret Verilog source"]
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["Compiler"
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(progn
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(setq verilog-tool 'verilog-compiler)
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(verilog-set-compile-command))
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:style radio
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:selected (equal verilog-tool `verilog-compiler)
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:help "When invoking compilation, compile Verilog source"]
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)
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("Move"
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["Beginning of function" verilog-beg-of-defun
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:keys "C-M-a"
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:help "Move backward to the beginning of the current function or procedure"]
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["End of function" verilog-end-of-defun
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:keys "C-M-e"
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:help "Move forward to the end of the current function or procedure"]
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["Mark function" verilog-mark-defun
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:keys "C-M-h"
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:help "Mark the current Verilog function or procedure"]
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["Goto function/module" verilog-goto-defun
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:help "Move to specified Verilog module/task/function"]
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["Move to beginning of block" electric-verilog-backward-sexp
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:help "Move backward over one balanced expression"]
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["Move to end of block" electric-verilog-forward-sexp
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:help "Move forward over one balanced expression"]
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)
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("Comments"
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["Comment Region" verilog-comment-region
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:help "Put marked area into a comment"]
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["UnComment Region" verilog-uncomment-region
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:help "Uncomment an area commented with Comment Region"]
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["Multi-line comment insert" verilog-star-comment
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:help "Insert Verilog /* */ comment at point"]
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["Lint error to comment" verilog-lint-off
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:help "Convert a Verilog linter warning line into a disable statement"]
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)
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"----"
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["Compile" compile
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:help "Perform compilation-action (above) on the current buffer"]
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["AUTO, Save, Compile" verilog-auto-save-compile
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:help "Recompute AUTOs, save buffer, and compile"]
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["Next Compile Error" next-error
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:help "Visit next compilation error message and corresponding source code"]
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["Ignore Lint Warning at point" verilog-lint-off
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:help "Convert a Verilog linter warning line into a disable statement"]
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"----"
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["Line up declarations around point" verilog-pretty-declarations
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:help "Line up declarations around point"]
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["Line up equations around point" verilog-pretty-expr
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:help "Line up expressions around point"]
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["Redo/insert comments on every end" verilog-label-be
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:help "Label matching begin ... end statements"]
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["Expand [x:y] vector line" verilog-expand-vector
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:help "Take a signal vector on the current line and expand it to multiple lines"]
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["Insert begin-end block" verilog-insert-block
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:help "Insert begin ... end"]
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["Complete word" verilog-complete-word
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:help "Complete word at point"]
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"----"
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["Recompute AUTOs" verilog-auto
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:help "Expand AUTO meta-comment statements"]
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["Kill AUTOs" verilog-delete-auto
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:help "Remove AUTO expansions"]
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["Inject AUTOs" verilog-inject-auto
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:help "Inject AUTOs into legacy non-AUTO buffer"]
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("AUTO Help..."
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["AUTO General" (describe-function 'verilog-auto)
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:help "Help introduction on AUTOs"]
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["AUTO Library Flags" (describe-variable 'verilog-library-flags)
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:help "Help on verilog-library-flags"]
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["AUTO Library Path" (describe-variable 'verilog-library-directories)
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:help "Help on verilog-library-directories"]
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["AUTO Library Files" (describe-variable 'verilog-library-files)
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:help "Help on verilog-library-files"]
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["AUTO Library Extensions" (describe-variable 'verilog-library-extensions)
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:help "Help on verilog-library-extensions"]
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["AUTO `define Reading" (describe-function 'verilog-read-defines)
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:help "Help on reading `defines"]
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["AUTO `include Reading" (describe-function 'verilog-read-includes)
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:help "Help on parsing `includes"]
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["AUTOARG" (describe-function 'verilog-auto-arg)
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:help "Help on AUTOARG - declaring module port list"]
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["AUTOASCIIENUM" (describe-function 'verilog-auto-ascii-enum)
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:help "Help on AUTOASCIIENUM - creating ASCII for enumerations"]
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["AUTOINOUTMODULE" (describe-function 'verilog-auto-inout-module)
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:help "Help on AUTOINOUTMODULE - copying i/o from another file"]
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["AUTOINOUT" (describe-function 'verilog-auto-inout)
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:help "Help on AUTOINOUT - adding inouts from cells"]
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["AUTOINPUT" (describe-function 'verilog-auto-input)
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:help "Help on AUTOINPUT - adding inputs from cells"]
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["AUTOINST" (describe-function 'verilog-auto-inst)
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:help "Help on AUTOINST - adding pins for cells"]
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["AUTOINST (.*)" (describe-function 'verilog-auto-star)
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:help "Help on expanding Verilog-2001 .* pins"]
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["AUTOINSTPARAM" (describe-function 'verilog-auto-inst-param)
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:help "Help on AUTOINSTPARAM - adding parameter pins to cells"]
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["AUTOOUTPUT" (describe-function 'verilog-auto-output)
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:help "Help on AUTOOUTPUT - adding outputs from cells"]
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["AUTOOUTPUTEVERY" (describe-function 'verilog-auto-output-every)
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:help "Help on AUTOOUTPUTEVERY - adding outputs of all signals"]
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["AUTOREG" (describe-function 'verilog-auto-reg)
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:help "Help on AUTOREG - declaring registers for non-wires"]
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["AUTOREGINPUT" (describe-function 'verilog-auto-reg-input)
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:help "Help on AUTOREGINPUT - declaring inputs for non-wires"]
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["AUTORESET" (describe-function 'verilog-auto-reset)
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:help "Help on AUTORESET - resetting always blocks"]
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["AUTOSENSE" (describe-function 'verilog-auto-sense)
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:help "Help on AUTOSENSE - sensitivity lists for always blocks"]
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["AUTOTIEOFF" (describe-function 'verilog-auto-tieoff)
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:help "Help on AUTOTIEOFF - tieing off unused outputs"]
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["AUTOUNUSED" (describe-function 'verilog-auto-unused)
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:help "Help on AUTOUNUSED - terminating unused inputs"]
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["AUTOWIRE" (describe-function 'verilog-auto-wire)
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:help "Help on AUTOWIRE - declaring wires for cells"]
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)
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"----"
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["Submit bug report" verilog-submit-bug-report
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:help "Submit via mail a bug report on verilog-mode.el"]
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["Version and FAQ" verilog-faq
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:help "Show the current version, and where to get the FAQ etc"]
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["Customize Verilog Mode..." verilog-customize
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:help "Customize variables and other settings used by Verilog-Mode"]
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["Customize Verilog Fonts & Colors" verilog-font-customize
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:help "Customize fonts used by Verilog-Mode."])))
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(easy-menu-define
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verilog-stmt-menu verilog-mode-map "Menu for statement templates in Verilog."
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'("Statements"
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["Header" verilog-sk-header t]
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["Comment" verilog-sk-comment t]
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"----"
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["Module" verilog-sk-module t]
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["Primitive" verilog-sk-primitive t]
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"----"
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["Input" verilog-sk-input t]
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["Output" verilog-sk-output t]
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["Inout" verilog-sk-inout t]
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["Wire" verilog-sk-wire t]
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["Reg" verilog-sk-reg t]
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["Define thing under point as a register" verilog-sk-define-signal t]
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"----"
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["Initial" verilog-sk-initial t]
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["Always" verilog-sk-always t]
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["Function" verilog-sk-function t]
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["Task" verilog-sk-task t]
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["Specify" verilog-sk-specify t]
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["Generate" verilog-sk-generate t]
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"----"
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["Begin" verilog-sk-begin t]
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["If" verilog-sk-if t]
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["(if) else" verilog-sk-else-if t]
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["For" verilog-sk-for t]
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["While" verilog-sk-while t]
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["Fork" verilog-sk-fork t]
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["Repeat" verilog-sk-repeat t]
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["Case" verilog-sk-case t]
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["Casex" verilog-sk-casex t]
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["Casez" verilog-sk-casez t]))
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(verilog-easy-menu-filter
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'("Statements"
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["Header" verilog-sk-header
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:help "Insert a header block at the top of file"]
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["Comment" verilog-sk-comment
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:help "Insert a comment block"]
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"----"
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["Module" verilog-sk-module
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:help "Insert a module .. (/*AUTOARG*/);.. endmodule block"]
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["Primitive" verilog-sk-primitive
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:help "Insert a primitive .. (.. );.. endprimitive block"]
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"----"
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["Input" verilog-sk-input
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:help "Insert an input declaration"]
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["Output" verilog-sk-output
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:help "Insert an output declaration"]
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["Inout" verilog-sk-inout
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:help "Insert an inout declaration"]
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["Wire" verilog-sk-wire
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:help "Insert a wire declaration"]
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["Reg" verilog-sk-reg
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:help "Insert a register declaration"]
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["Define thing under point as a register" verilog-sk-define-signal
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:help "Define signal under point as a register at the top of the module"]
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"----"
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["Initial" verilog-sk-initial
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:help "Insert an initial begin .. end block"]
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["Always" verilog-sk-always
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:help "Insert an always @(AS) begin .. end block"]
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["Function" verilog-sk-function
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:help "Insert a function .. begin .. end endfunction block"]
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["Task" verilog-sk-task
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:help "Insert a task .. begin .. end endtask block"]
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["Specify" verilog-sk-specify
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:help "Insert a specify .. endspecify block"]
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["Generate" verilog-sk-generate
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:help "Insert a generate .. endgenerate block"]
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"----"
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["Begin" verilog-sk-begin
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:help "Insert a begin .. end block"]
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["If" verilog-sk-if
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:help "Insert an if (..) begin .. end block"]
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["(if) else" verilog-sk-else-if
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:help "Insert an else if (..) begin .. end block"]
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["For" verilog-sk-for
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:help "Insert a for (...) begin .. end block"]
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["While" verilog-sk-while
|
||||
:help "Insert a while (...) begin .. end block"]
|
||||
["Fork" verilog-sk-fork
|
||||
:help "Insert a fork begin .. end .. join block"]
|
||||
["Repeat" verilog-sk-repeat
|
||||
:help "Insert a repeat (..) begin .. end block"]
|
||||
["Case" verilog-sk-case
|
||||
:help "Insert a case block, prompting for details"]
|
||||
["Casex" verilog-sk-casex
|
||||
:help "Insert a casex (...) item: begin.. end endcase block"]
|
||||
["Casez" verilog-sk-casez
|
||||
:help "Insert a casez (...) item: begin.. end endcase block"])))
|
||||
|
||||
(defvar verilog-mode-abbrev-table nil
|
||||
"Abbrev table in use in Verilog-mode buffers.")
|
||||
|
|
@ -1129,7 +1235,7 @@ will break, as the o's continuously replace. xa -> x works ok though."
|
|||
(defsubst verilog-re-search-forward (REGEXP BOUND NOERROR)
|
||||
; checkdoc-params: (REGEXP BOUND NOERROR)
|
||||
"Like `re-search-forward', but skips over match in comments or strings."
|
||||
(store-match-data '(nil nil))
|
||||
(store-match-data '(nil nil)) ;; So match-end will return nil if no matches found
|
||||
(while (and
|
||||
(re-search-forward REGEXP BOUND NOERROR)
|
||||
(and (verilog-skip-forward-comment-or-string)
|
||||
|
|
@ -1143,7 +1249,7 @@ will break, as the o's continuously replace. xa -> x works ok though."
|
|||
(defsubst verilog-re-search-backward (REGEXP BOUND NOERROR)
|
||||
; checkdoc-params: (REGEXP BOUND NOERROR)
|
||||
"Like `re-search-backward', but skips over match in comments or strings."
|
||||
(store-match-data '(nil nil))
|
||||
(store-match-data '(nil nil)) ;; So match-end will return nil if no matches found
|
||||
(while (and
|
||||
(re-search-backward REGEXP BOUND NOERROR)
|
||||
(and (verilog-skip-backward-comment-or-string)
|
||||
|
|
@ -2008,13 +2114,13 @@ Use filename, if current buffer being edited shorten to just buffer name."
|
|||
":" (int-to-string (count-lines (point-min) (or pointnum (point))))))
|
||||
|
||||
(defun electric-verilog-backward-sexp ()
|
||||
"Move backward over a sexp."
|
||||
"Move backward over one balanced expression."
|
||||
(interactive)
|
||||
;; before that see if we are in a comment
|
||||
(verilog-backward-sexp))
|
||||
|
||||
(defun electric-verilog-forward-sexp ()
|
||||
"Move forward over a sexp."
|
||||
"Move forward over one balanced expression."
|
||||
(interactive)
|
||||
;; before that see if we are in a comment
|
||||
(verilog-forward-sexp))
|
||||
|
|
@ -2312,15 +2418,15 @@ Some other functions are:
|
|||
|
||||
\\[verilog-comment-region] Put marked area in a comment.
|
||||
\\[verilog-uncomment-region] Uncomment an area commented with \\[verilog-comment-region].
|
||||
\\[verilog-insert-block] Insert begin ... end;.
|
||||
\\[verilog-insert-block] Insert begin ... end.
|
||||
\\[verilog-star-comment] Insert /* ... */.
|
||||
|
||||
\\[verilog-sk-always] Insert a always @(AS) begin .. end block.
|
||||
\\[verilog-sk-always] Insert an always @(AS) begin .. end block.
|
||||
\\[verilog-sk-begin] Insert a begin .. end block.
|
||||
\\[verilog-sk-case] Insert a case block, prompting for details.
|
||||
\\[verilog-sk-for] Insert a for (...) begin .. end block, prompting for details.
|
||||
\\[verilog-sk-generate] Insert a generate .. endgenerate block.
|
||||
\\[verilog-sk-header] Insert a nice header block at the top of file.
|
||||
\\[verilog-sk-header] Insert a header block at the top of file.
|
||||
\\[verilog-sk-initial] Insert an initial begin .. end block.
|
||||
\\[verilog-sk-fork] Insert a fork begin .. end .. join block.
|
||||
\\[verilog-sk-module] Insert a module .. (/*AUTOARG*/);.. endmodule block.
|
||||
|
|
@ -4409,7 +4515,7 @@ Optional BOUND limits search."
|
|||
(let ((state (save-excursion (verilog-syntax-ppss))))
|
||||
(cond
|
||||
((nth 3 state) ;Inside string
|
||||
(goto-char (nth 3 state))
|
||||
(search-forward "\"")
|
||||
t)
|
||||
((nth 7 state) ;Inside // comment
|
||||
(forward-line 1)
|
||||
|
|
@ -6258,7 +6364,7 @@ Outputs comments above subcell signals, for example:
|
|||
;; below 3 modified by verilog-read-sub-decls-line
|
||||
sigs-out sigs-inout sigs-in)
|
||||
(verilog-beg-of-defun)
|
||||
(while (re-search-forward "\\(/\\*AUTOINST\\*/\\|\\.\\*\\)" end-mod-point t)
|
||||
(while (verilog-re-search-forward "\\(/\\*AUTOINST\\*/\\|\\.\\*\\)" end-mod-point t)
|
||||
(save-excursion
|
||||
(goto-char (match-beginning 0))
|
||||
(unless (verilog-inside-comment-p)
|
||||
|
|
@ -7275,23 +7381,15 @@ and invalidating the cache."
|
|||
;; Auto creation utilities
|
||||
;;
|
||||
|
||||
(defun verilog-auto-re-search-do (search-for func)
|
||||
"Search for the given auto text regexp SEARCH-FOR, and perform FUNC where it occurs."
|
||||
(goto-char (point-min))
|
||||
(while (verilog-re-search-forward search-for nil t)
|
||||
(funcall func)))
|
||||
|
||||
(defun verilog-auto-search-do (search-for func)
|
||||
"Search for the given auto text SEARCH-FOR, and perform FUNC where it occurs."
|
||||
(goto-char (point-min))
|
||||
(while (search-forward search-for nil t)
|
||||
(if (not (save-excursion
|
||||
(goto-char (match-beginning 0))
|
||||
(verilog-inside-comment-p)))
|
||||
(funcall func))))
|
||||
|
||||
(defun verilog-auto-re-search-do (search-for func)
|
||||
"Search for the given auto text SEARCH-FOR, and perform FUNC where it occurs."
|
||||
(goto-char (point-min))
|
||||
(while (re-search-forward search-for nil t)
|
||||
(if (not (save-excursion
|
||||
(goto-char (match-beginning 0))
|
||||
(verilog-inside-comment-p)))
|
||||
(funcall func))))
|
||||
(verilog-auto-re-search-do (regexp-quote search-for) func))
|
||||
|
||||
(defun verilog-insert-one-definition (sig type indent-pt)
|
||||
"Print out a definition for SIG of the given TYPE,
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue