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Port instruction stepper to x64 with stub instruction decode
Copied from Perforce Change: 178320 ServerID: perforce.ravenbrook.com
This commit is contained in:
David Lovemore
parent
0ea1ae3aba
commit
1184e96675
4 changed files with 49 additions and 202 deletions
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@ -1,4 +1,4 @@
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/* prmci3.h: PROTECTION MUTATOR CONTEXT (Intel 386)
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/* prmci6.h: PROTECTION MUTATOR CONTEXT (x64)
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*
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* $Id$
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* Copyright (c) 2001 Ravenbrook Limited. See end of file for license.
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@ -6,21 +6,21 @@
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* .readership: MPS developers.
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*/
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#ifndef prmci3_h
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#define prmci3_h
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#ifndef prmci6_h
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#define prmci6_h
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#include "mpm.h"
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typedef Word *MRef; /* pointer to a machine word */
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MRef Prmci3AddressHoldingReg(MutatorFaultContext, unsigned int);
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MRef Prmci6AddressHoldingReg(MutatorFaultContext, unsigned int);
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void Prmci3DecodeFaultContext(MRef *, Byte **, MutatorFaultContext);
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void Prmci6DecodeFaultContext(MRef *, Byte **, MutatorFaultContext);
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void Prmci3StepOverIns(MutatorFaultContext, Size);
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void Prmci6StepOverIns(MutatorFaultContext, Size);
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#endif /* prmci3_h */
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#endif /* prmci6_h */
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/* C. COPYRIGHT AND LICENSE
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@ -1,4 +1,4 @@
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/* prmci3w3.c: PROTECTION MUTATOR CONTEXT INTEL 386 (Win32)
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/* prmci6w3.c: PROTECTION MUTATOR CONTEXT INTEL 386 (Win32)
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*
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* $Id$
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* Copyright (c) 2001 Ravenbrook Limited. See end of file for license.
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@ -10,8 +10,6 @@
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*
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* SOURCES
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*
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* .source.i486: Intel486 Microprocessor Family Programmer's
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* Reference Manual (book.intel92).
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*
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* ASSUMPTIONS
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*
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@ -20,41 +18,49 @@
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*/
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#include "prmcw3.h"
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#include "prmci3.h"
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#include "prmci6.h"
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#include "mpm.h"
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SRCID(prmci3w3, "$Id$");
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SRCID(prmci6w3, "$Id$");
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/* Prmci3AddressHoldingReg -- Return an address for a given machine register */
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/* Prmci6AddressHoldingReg -- Return an address for a given machine register */
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MRef Prmci3AddressHoldingReg(MutatorFaultContext context, unsigned int regnum)
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MRef Prmci6AddressHoldingReg(MutatorFaultContext context, unsigned int regnum)
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{
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PCONTEXT wincont;
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AVER(regnum <= 7);
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AVER(regnum <= 16);
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AVER(regnum >= 0);
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wincont = context->ep->ContextRecord;
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switch (regnum) {
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case 0: return (MRef)&wincont->Eax;
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case 1: return (MRef)&wincont->Ecx;
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case 2: return (MRef)&wincont->Edx;
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case 3: return (MRef)&wincont->Ebx;
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case 4: return (MRef)&wincont->Esp;
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case 5: return (MRef)&wincont->Ebp;
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case 6: return (MRef)&wincont->Esi;
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case 7: return (MRef)&wincont->Edi;
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case 0: return (MRef)&wincont->Rax;
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case 1: return (MRef)&wincont->Rcx;
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case 2: return (MRef)&wincont->Rdx;
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case 3: return (MRef)&wincont->Rbx;
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case 4: return (MRef)&wincont->Rsp;
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case 5: return (MRef)&wincont->Rbp;
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case 6: return (MRef)&wincont->Rsi;
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case 7: return (MRef)&wincont->Rdi;
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case 8: return (MRef)&wincont->R8;
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case 9: return (MRef)&wincont->R9;
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case 10: return (MRef)&wincont->R10;
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case 11: return (MRef)&wincont->R11;
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case 12: return (MRef)&wincont->R12;
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case 13: return (MRef)&wincont->R13;
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case 14: return (MRef)&wincont->R14;
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case 15: return (MRef)&wincont->R15;
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}
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NOTREACHED;
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return NULL; /* suppress warning */
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}
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/* Prmci3DecodeFaultContext -- decode fault context */
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/* Prmci6DecodeFaultContext -- decode fault context */
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void Prmci3DecodeFaultContext(MRef *faultmemReturn, Byte **insvecReturn,
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void Prmci6DecodeFaultContext(MRef *faultmemReturn, Byte **insvecReturn,
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MutatorFaultContext context)
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{
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LPEXCEPTION_RECORD er;
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@ -66,15 +72,15 @@ void Prmci3DecodeFaultContext(MRef *faultmemReturn, Byte **insvecReturn,
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AVER(er->ExceptionCode == EXCEPTION_ACCESS_VIOLATION);
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*faultmemReturn = (MRef)er->ExceptionInformation[1];
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*insvecReturn = (Byte*)context->ep->ContextRecord->Eip;
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*insvecReturn = (Byte*)context->ep->ContextRecord->Rip;
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}
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/* Prmci3StepOverIns -- skip an instruction by changing the context */
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/* Prmci6StepOverIns -- skip an instruction by changing the context */
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void Prmci3StepOverIns(MutatorFaultContext context, Size inslen)
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void Prmci6StepOverIns(MutatorFaultContext context, Size inslen)
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{
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context->ep->ContextRecord->Eip += (DWORD)inslen;
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context->ep->ContextRecord->Rip += (DWORD64)inslen;
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}
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@ -1,4 +1,4 @@
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/* proti3.c: PROTECTION MUTATOR CONTEXT (INTEL 386)
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/* proti6.c: PROTECTION MUTATOR CONTEXT (x64)
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*
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* $Id$
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* Copyright (c) 2001 Ravenbrook Limited. See end of file for license.
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@ -10,23 +10,12 @@
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* .purpose: This module implements the part of the protection module
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* that implements the MutatorFaultContext type.
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*
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* .requirements: Current requirements are for limited support only, for
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* stepping the sorts of instructions that the Dylan compiler might
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* generate for table vector access - i.e., a restricted subset of MOV
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* addressing modes. This avoids the need to scan entire weak tables at
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* an inappropriate rank when a page fault occurs.
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*
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*
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* SOURCES
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*
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* .source.i486: Intel486 Microprocessor Family Programmer's
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* Reference Manual
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*
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* .source.dylan: Dylan table code implementation. Especially the
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* following HOPE units:
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* D-lib-dylan!table.dylan (class <entry-vector>, slot entry-element)
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* D-dfmc-harp-cg!harp-primitives.dylan (method op--repeated-slot-element)
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* D-harp-pentium-harp!moves.dylan (pentium-template ld-index)
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* .source.amd64: AMD64 Architecture Programmer’s Manual Volume 3:
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* General-Purpose and System Instructions
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* <http://support.amd.com/us/Processor_TechDocs/24594_APM_v3.pdf>
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*
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*
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* ASSUMPTIONS
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@ -35,140 +24,12 @@
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* ResUNIMPL. A null implementation of this module would be overly
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* conservative but otherwise correct.
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*
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* .assume.want: The Dylan implementation is likely to access a
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* weak table vector using either MOV r/m32,r32 or MOV r32,r/m32
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* instructions, where the r/m32 operand will be of one of the forms
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* disp8[reg], disp8[reg1][reg2], disp8[reg1][reg2*4] (see .source.dylan
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* and .source.i486)
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*
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* .assume.i3: Assume the following about the i386 environment:
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* Steppable instructions (.assume.want) use the CS, DS & SS
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* segment registers only (see .source.i486 Table 2-3).
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* The procesor runs in 32 bit mode.
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* The CS, DS and SS segment registers all describe identical 32-
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* bit flat address spaces.
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*/
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#include "mpm.h"
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#include "prmci3.h"
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#include "prmci6.h"
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SRCID(proti3, "$Id$");
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/* DecodeCB -- Decode an Intel x86 control byte into Hi, Medium & Low fields */
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static void DecodeCB(unsigned int *hReturn,
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unsigned int *mReturn,
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unsigned int *lReturn,
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Byte op)
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{
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/* see .source.i486 Figure 26-2 */
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unsigned int uop = (unsigned int)op;
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*lReturn = uop & 7;
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uop = uop >> 3;
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*mReturn = uop & 7;
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uop = uop >> 3;
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*hReturn = uop & 3;
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}
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/* DecodeSIB -- Decode a Scale Index Base byte for an Intel x86 instruction */
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static void DecodeSIB(unsigned int *sReturn,
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unsigned int *iReturn,
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unsigned int *bReturn,
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Byte op)
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{
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DecodeCB(sReturn, iReturn, bReturn, op);
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}
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/* DecodeModRM -- Decode a ModR/M byte for an Intel x86 instruction */
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static void DecodeModRM(unsigned int *modReturn,
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unsigned int *rReturn,
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unsigned int *mReturn,
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Byte op)
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{
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DecodeCB(modReturn, rReturn, mReturn, op);
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}
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/* RegValue -- Return the value of a machine register from a context */
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static Word RegValue(MutatorFaultContext context, unsigned int regnum)
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{
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MRef addr;
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addr = Prmci3AddressHoldingReg(context, regnum);
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return *addr;
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}
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/* Return a byte element of an instruction vector as a
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* Word value, with sign extension
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*/
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static Word SignedInsElt(Byte insvec[], Count i)
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{
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signed char eltb;
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eltb = ((signed char*)insvec)[i];
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return (Word)eltb;
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}
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/* If a MOV instruction is a sufficiently simple example of a
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* move between a register and memory (in either direction),
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* then find the register, the effective address and the size
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* of the instruction. The instruction is considered sufficiently
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* simple if it uses a single byte displacement, a base register,
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* and either no index or a (possibly scaled) register.
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*/
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static Bool DecodeSimpleMov(unsigned int *regnumReturn,
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MRef *memReturn,
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Size *inslenReturn,
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MutatorFaultContext context,
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Byte insvec[])
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{
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unsigned int mod;
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unsigned int r;
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unsigned int m;
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DecodeModRM(&mod, &r, &m, insvec[1]); /* .source.i486 Table 26-3 */
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if(1 == mod) {
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/* Only know about single byte displacements, .assume.want */
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Word base;
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Word index;
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Word disp;
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if(4 == m) {
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/* There is an index. */
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unsigned int s;
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unsigned int i;
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unsigned int b;
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DecodeSIB(&s, &i, &b, insvec[2]); /* .source.i486 Table 26-3 */
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if(4 == i) {
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return FALSE; /* degenerate SIB form - unused by Dylan compiler */
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}
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disp = SignedInsElt(insvec, 3);
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base = RegValue(context, b);
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index = RegValue(context, i) << s;
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*inslenReturn = 4;
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} else {
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/* MOV with reg1 & [reg2+byte] parameters */
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disp = SignedInsElt(insvec, 2);
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base = RegValue(context, m);
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index = 0;
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*inslenReturn = 3;
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}
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*regnumReturn = r;
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*memReturn = (MRef)(base + index + disp); /* .assume.i3 */
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return TRUE;
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}
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return FALSE;
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}
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SRCID(proti6, "$Id$");
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static Bool IsSimpleMov(Size *inslenReturn,
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MutatorFaultContext context)
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{
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Byte *insvec;
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unsigned int regnum;
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MRef mem;
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MRef faultmem;
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Prmci3DecodeFaultContext(&faultmem, &insvec, context);
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/* .assume.want */
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/* .source.i486 Page 26-210 */
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if((Byte)0x8b == insvec[0]) {
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/* This is an instruction of type MOV reg, r/m32 */
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if(DecodeSimpleMov(®num, &mem, inslenReturn, context, insvec)) {
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AVER(faultmem == mem); /* Ensure computed address matches exception */
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*srcReturn = mem;
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*destReturn = Prmci3AddressHoldingReg(context, regnum);
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return TRUE;
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}
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} else if((Byte)0x89 == insvec[0]) {
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/* This is an instruction of type MOV r/m32, reg */
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if(DecodeSimpleMov(®num, &mem, inslenReturn, context, insvec)) {
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AVER(faultmem == mem); /* Ensure computed address matches exception */
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*destReturn = mem;
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*srcReturn = Prmci3AddressHoldingReg(context, regnum);
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return TRUE;
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}
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}
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Prmci6DecodeFaultContext(&faultmem, &insvec, context);
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/* Unimplemented */
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UNUSED(inslenReturn);
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UNUSED(srcReturn);
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UNUSED(destReturn);
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return FALSE;
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}
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@ -214,7 +57,6 @@ Bool ProtCanStepInstruction(MutatorFaultContext context)
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MRef dest;
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/* .assume.null */
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/* .assume.want */
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if(IsSimpleMov(&inslen, &src, &dest, context)) {
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return TRUE;
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}
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@ -230,10 +72,9 @@ Res ProtStepInstruction(MutatorFaultContext context)
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MRef dest;
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/* .assume.null */
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/* .assume.want */
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if(IsSimpleMov(&inslen, &src, &dest, context)) {
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*dest = *src;
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Prmci3StepOverIns(context, inslen);
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Prmci6StepOverIns(context, inslen);
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return ResOK;
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}
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@ -20,7 +20,7 @@ MPM = <ring> <mpm> <bt> <protocol> <boot> \
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<arenavm> <arenacl> <locus> <arena> <global> <tract> <reserv> \
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<pool> <poolabs> <poolmfs> <poolmv> \
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<root> <format> <buffer> <walk> <lockw3> \
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<ref> <trace> <traceanc> <prmcan> <protw3> \
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<ref> <trace> <traceanc> <protw3> <proti6> <prmci6w3> \
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<shield> <vmw3> \
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<thw3> <thw3i6> <ssw3i6> <mpsi> <mpsiw3> <ld> <span> \
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<event> <seg> <sac> <poolmrg> <message> <dbgpool> <dbgpooli> \
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