⚡️ STM32H7 Serial DMA (#27633)
This commit is contained in:
rondlh
GitHub
parent
0a598071af
commit
7f598ae66d
3 changed files with 182 additions and 104 deletions
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@ -37,7 +37,17 @@
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#include "HardwareSerial.h"
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#include "uart.h"
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// USART/UART PIN MAPPING FOR STM32F0/F1/F2/F4/F7
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// Prevent selection of LPUART1 on STM32H7xx
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#if defined(STM32H7xx) && (PIN_SERIAL1_TX == PA_9)
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#undef PIN_SERIAL1_TX
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#define PIN_SERIAL1_TX PA_9_ALT1
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#endif
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#if defined(STM32H7xx) && (PIN_SERIAL1_RX == PA_10)
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#undef PIN_SERIAL1_RX
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#define PIN_SERIAL1_RX PA_10_ALT1
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#endif
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// USART/UART pin mapping for STM32F0/F1/F2/F4/F7/H7
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#ifndef PIN_SERIAL1_TX
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#define PIN_SERIAL1_TX PA9
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#endif
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@ -75,46 +85,6 @@
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#define PIN_SERIAL6_RX PC7
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#endif
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// TODO: Get from include file
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#if ANY(STM32F2xx, STM32F4xx, STM32F7xx)
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#define RCC_AHB1Periph_DMA1 ((uint32_t)0x00200000)
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#define RCC_AHB1Periph_DMA2 ((uint32_t)0x00400000)
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void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState) {
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// Check the parameters
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assert_param(IS_RCC_AHB1_CLOCK_PERIPH(RCC_AHB1Periph));
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assert_param(IS_FUNCTIONAL_STATE(NewState));
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if (NewState != DISABLE)
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RCC->AHB1ENR |= RCC_AHB1Periph;
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else
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RCC->AHB1ENR &= ~RCC_AHB1Periph;
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}
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#endif
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#if ANY(STM32F0xx, STM32F1xx)
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#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001)
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#define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002)
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void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) {
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/* Check the parameters */
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assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
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assert_param(IS_FUNCTIONAL_STATE(NewState));
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if (NewState != DISABLE)
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RCC->AHBENR |= RCC_AHBPeriph;
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else
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RCC->AHBENR &= ~RCC_AHBPeriph;
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}
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#endif
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// END OF TODO------------------------------------------------------
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// SerialEvent functions are weak, so when the user doesn't define them,
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// the linker just sets their address to 0 (which is checked below).
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#ifdef USING_HW_SERIAL1
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@ -161,11 +131,12 @@ HAL_HardwareSerial::HAL_HardwareSerial(void *peripheral) {
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setRx(PIN_SERIAL1_RX);
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setTx(PIN_SERIAL1_TX);
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_uart_index = 0;
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#ifdef DMA2_Stream2
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RX_DMA = { USART1, RCC_AHB1Periph_DMA2, 4, DMA2_Stream2 };
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#ifdef DMA2_Stream2 // F2 / F4 / F7 / H7
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RX_DMA = { USART1, 2, DMA2_Stream2 }; // USART, DMA controller no., DMA stream
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#endif
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#ifdef DMA1_Channel5
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RX_DMA = { USART1, RCC_AHBPeriph_DMA1, DMA1, DMA1_Channel5 };
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#ifdef DMA1_Channel5 // F0 / F1
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RX_DMA = { USART1, 1, DMA1_Channel5 }; // USART, DMA controller no., DMA channel
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#endif
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}
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else if (peripheral == USART2) {
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@ -173,10 +144,10 @@ HAL_HardwareSerial::HAL_HardwareSerial(void *peripheral) {
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setTx(PIN_SERIAL2_TX);
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_uart_index = 1;
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#ifdef DMA1_Stream5
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RX_DMA = { USART2, RCC_AHB1Periph_DMA1, 4, DMA1_Stream5 };
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RX_DMA = { USART2, 1, DMA1_Stream5 };
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#endif
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#ifdef DMA1_Channel6
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RX_DMA = { USART2, RCC_AHBPeriph_DMA1, DMA1, DMA1_Channel6 };
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RX_DMA = { USART2, 1, DMA1_Channel6 };
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#endif
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}
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else if (peripheral == USART3) {
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@ -184,17 +155,17 @@ HAL_HardwareSerial::HAL_HardwareSerial(void *peripheral) {
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setTx(PIN_SERIAL3_TX);
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_uart_index = 2;
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#ifdef DMA1_Stream1
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RX_DMA = { USART3, RCC_AHB1Periph_DMA1, 4, DMA1_Stream1 };
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RX_DMA = { USART3, 1, DMA1_Stream1 };
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#endif
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#ifdef DMA1_Channel3 // F0 has no support for UART3, requires system remapping
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RX_DMA = { USART3, RCC_AHBPeriph_DMA1, DMA1, DMA1_Channel3 };
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RX_DMA = { USART3, 1, DMA1_Channel3 };
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#endif
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}
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#ifdef USART4 // Only F2 / F4 / F7
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else if (peripheral == USART4) {
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#ifdef DMA1_Stream2
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RX_DMA = { USART4, RCC_AHB1Periph_DMA1, 4, DMA1_Stream2 };
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RX_DMA = { USART4, 1, DMA1_Stream2 };
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#endif
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setRx(PIN_SERIAL4_RX);
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setTx(PIN_SERIAL4_TX);
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@ -205,10 +176,10 @@ HAL_HardwareSerial::HAL_HardwareSerial(void *peripheral) {
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#ifdef UART4
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else if (peripheral == UART4) {
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#ifdef DMA1_Stream2
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RX_DMA = { UART4, RCC_AHB1Periph_DMA1, 4, DMA1_Stream2 };
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RX_DMA = { UART4, 1, DMA1_Stream2 };
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#endif
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#ifdef DMA2_Channel3 // STM32F0xx has only 3 UARTs
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RX_DMA = { UART4, RCC_AHBPeriph_DMA2, DMA2, DMA2_Channel3 };
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RX_DMA = { UART4, 2, DMA2_Channel3 };
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#endif
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setRx(PIN_SERIAL4_RX);
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setTx(PIN_SERIAL4_TX);
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@ -216,10 +187,10 @@ HAL_HardwareSerial::HAL_HardwareSerial(void *peripheral) {
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}
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#endif
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#ifdef UART5 // Only F2 / F4 / F7
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#ifdef UART5 // Only F2 / F4 / F7 / H7
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else if (peripheral == UART5) {
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#ifdef DMA1_Stream0
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RX_DMA = { UART5, RCC_AHB1Periph_DMA1, 4, DMA1_Stream0 };
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RX_DMA = { UART5, 1, DMA1_Stream0 };
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#endif
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setRx(PIN_SERIAL5_RX);
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setTx(PIN_SERIAL5_TX);
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@ -227,10 +198,10 @@ HAL_HardwareSerial::HAL_HardwareSerial(void *peripheral) {
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}
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#endif
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#ifdef USART6 // Only F2 / F4 / F7
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#ifdef USART6 // Only F2 / F4 / F7 / H7
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else if (peripheral == USART6) {
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#ifdef DMA2_Stream1
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RX_DMA = { USART6, RCC_AHB1Periph_DMA2, 4, DMA2_Stream1 };
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RX_DMA = { USART6, 2, DMA2_Stream1 };
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#endif
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setRx(PIN_SERIAL6_RX);
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setTx(PIN_SERIAL6_TX);
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@ -271,14 +242,34 @@ void HAL_HardwareSerial::init(PinName _rx, PinName _tx) {
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* @param obj : pointer to serial_t structure
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* @retval last character received
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*/
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int HAL_HardwareSerial::_tx_complete_irq(serial_t *obj) {
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// If interrupts are enabled, there must be more data in the output buffer. Send the next byte
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obj->tx_tail = (obj->tx_tail + 1) % TX_BUFFER_SIZE;
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if (obj->tx_head == obj->tx_tail) return -1;
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#if DISABLED(STM32H7xx)
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return 0;
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}
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int HAL_HardwareSerial::_tx_complete_irq(serial_t *obj) {
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// If interrupts are enabled, there must be more data in the output buffer. Send the next byte
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obj->tx_tail = (obj->tx_tail + 1) % TX_BUFFER_SIZE;
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if (obj->tx_head == obj->tx_tail)
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return -1;
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return 0;
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}
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#else // STM32H7xx, has different uart_attach_tx_callback
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int HAL_HardwareSerial::_tx_complete_irq(serial_t *obj) {
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// If interrupts are enabled, there must be more data in the output buffer. Send the next byte
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obj->tx_tail = (obj->tx_tail + obj->tx_size) % TX_BUFFER_SIZE;
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if (obj->tx_head != obj->tx_tail) {
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size_t remaining_data = (TX_BUFFER_SIZE + obj->tx_head - obj->tx_tail) % TX_BUFFER_SIZE;
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obj->tx_size = min(remaining_data, (size_t)(TX_BUFFER_SIZE - obj->tx_tail));
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uart_attach_tx_callback(obj, _tx_complete_irq, obj->tx_size);
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return -1;
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}
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return 0;
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}
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#endif
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// Public Methods //////////////////////////////////////////////////////////////
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@ -340,7 +331,7 @@ void HAL_HardwareSerial::update_rx_head() {
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}
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#endif
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#if ANY(STM32F2xx, STM32F4xx, STM32F7xx)
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#if ANY(STM32F2xx, STM32F4xx, STM32F7xx, STM32H7xx)
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_serial.rx_head = RX_BUFFER_SIZE - RX_DMA.dma_streamRX->NDTR;
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#endif
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@ -352,18 +343,22 @@ void HAL_HardwareSerial::update_rx_head() {
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int HAL_HardwareSerial::available() {
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update_rx_head();
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return ((unsigned int)(RX_BUFFER_SIZE + _serial.rx_head - _serial.rx_tail)) % RX_BUFFER_SIZE;
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}
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int HAL_HardwareSerial::peek() {
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update_rx_head();
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if (_serial.rx_head == _serial.rx_tail) return -1;
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if (_serial.rx_head == _serial.rx_tail)
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return -1;
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return _serial.rx_buff[_serial.rx_tail];
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}
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int HAL_HardwareSerial::read() {
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update_rx_head();
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if (_serial.rx_head == _serial.rx_tail) return -1; // No chars if the head isn't ahead of the tail
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if (_serial.rx_head == _serial.rx_tail)
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return -1; // No chars if the head isn't ahead of the tail
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unsigned char c = _serial.rx_buff[_serial.rx_tail];
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_serial.rx_tail = (rx_buffer_index_t)(_serial.rx_tail + 1) % RX_BUFFER_SIZE;
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@ -380,8 +375,18 @@ size_t HAL_HardwareSerial::write(uint8_t c) { // Interrupt based wri
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_serial.tx_buff[_serial.tx_head] = c;
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_serial.tx_head = i;
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if (!serial_tx_active(&_serial))
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uart_attach_tx_callback(&_serial, _tx_complete_irq); // Write next byte, launch interrupt
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#ifdef STM32H7xx // Support STM32H7xx with different uart_attach_tx_callback
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if ((!serial_tx_active(&_serial)) && (_serial.tx_head != _serial.tx_tail)) {
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size_t remaining_data = (TX_BUFFER_SIZE + _serial.tx_head -_serial.tx_tail) % TX_BUFFER_SIZE;
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_serial.tx_size = min(remaining_data, (size_t)(TX_BUFFER_SIZE - _serial.tx_tail));
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uart_attach_tx_callback(&_serial, _tx_complete_irq, _serial.tx_size);
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return -1;
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}
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#else
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if (!serial_tx_active(&_serial))
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uart_attach_tx_callback(&_serial, _tx_complete_irq); // Write next byte, launch interrupt
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#endif
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return 1;
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}
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@ -390,57 +395,132 @@ void HAL_HardwareSerial::flush() {
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while ((_serial.tx_head != _serial.tx_tail)) { /* nada */ } // nop, the interrupt handler will free up space for us
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}
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#if ANY(STM32F2xx, STM32F4xx, STM32F7xx)
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#if ANY(STM32F2xx, STM32F4xx, STM32F7xx, STM32H7xx)
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void HAL_HardwareSerial::Serial_DMA_Read_Enable() {
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RCC_AHB1PeriphClockCmd(RX_DMA.dma_rcc, ENABLE); // Enable DMA clock
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#ifdef STM32F7xx
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RX_DMA.dma_streamRX->PAR = (uint32_t)(&RX_DMA.uart->RDR); // RX peripheral receive address (usart) F7
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if (RX_DMA.DMA_ID == 1)
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__HAL_RCC_DMA1_CLK_ENABLE(); // Enable DMA1 clock
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else
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__HAL_RCC_DMA2_CLK_ENABLE(); // Enable DMA2 clock
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// Reset DMA, wait if needed to complete the running process
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RX_DMA.dma_streamRX->CR = 0; // DMA stream clear/disable
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while (RX_DMA.dma_streamRX->CR & DMA_SxCR_EN) { /* just wait for DMA to complete */ }
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// UART clear/disable
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RX_DMA.uart->CR1 = 0;
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// Configure DMA
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#if ANY(STM32F7xx, STM32H7xx) // F7 and H7 use RDR (Receive Data Register)
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RX_DMA.dma_streamRX->PAR = (uint32_t)(&RX_DMA.uart->RDR); // DMA stream Peripheral Address Register = USART Data Register
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#else
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RX_DMA.dma_streamRX->PAR = (uint32_t)(&RX_DMA.uart->DR); // RX peripheral address (usart) F2 / F4
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RX_DMA.dma_streamRX->PAR = (uint32_t)(&RX_DMA.uart->DR); // DMA stream Peripheral Address Register = USART Data Register
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#endif
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RX_DMA.dma_streamRX->M0AR = (uint32_t)_serial.rx_buff; // RX destination address (memory)
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RX_DMA.dma_streamRX->NDTR = RX_BUFFER_SIZE; // RX buffer size
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RX_DMA.dma_streamRX->CR = (RX_DMA.dma_channel << 25); // RX channel selection, set to 0 all the other CR bits
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RX_DMA.dma_streamRX->M0AR = (uint32_t)_serial.rx_buff; // DMA stream Memory 0 Adress Register = RX buffer address
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RX_DMA.dma_streamRX->NDTR = RX_BUFFER_SIZE; // DMA stream Number of Data Transfer Register
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RX_DMA.dma_streamRX->CR |= (3 << 16); // RX priority level: Very High
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#if DISABLED(STM32H7xx) // Select channel via CR register
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//RX_DMA.dma_streamRX->CR &= ~(3 << 13); // RX memory data size: 8 bit
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//RX_DMA.dma_streamRX->CR &= ~(3 << 11); // RX peripheral data size: 8 bit
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RX_DMA.dma_streamRX->CR |= (1 << 10); // RX memory increment mode
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//RX_DMA.dma_streamRX->CR &= ~(1 << 9); // RX peripheral no increment mode
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RX_DMA.dma_streamRX->CR |= (1 << 8); // RX circular mode enabled
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//RX_DMA.dma_streamRX->CR &= ~(1 << 6); // RX data transfer direction: Peripheral-to-memory
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RX_DMA.uart->CR3 |= (1 << 6); // Enable DMA receiver (DMAR)
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RX_DMA.dma_streamRX->CR |= (1 << 0); // RX enable DMA
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RX_DMA.dma_streamRX->CR = 4 << DMA_SxCR_CHSEL_Pos; // DMA stream Channel Selection, always use channel 4
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#else // STM32H7xx, select channel with DMAMUX1, channel DMA1 is channel DMAMUX, channel DMA2 is channel DMAMUX + 8
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if (RX_DMA.uart == USART1) DMAMUX1_Channel10->CCR |= DMA_REQUEST_USART1_RX; // DMA2, Stream 2
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if (RX_DMA.uart == USART2) DMAMUX1_Channel5->CCR |= DMA_REQUEST_USART2_RX; // DMA1, Stream 5
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if (RX_DMA.uart == USART3) DMAMUX1_Channel1->CCR |= DMA_REQUEST_USART3_RX; // DMA1, Stream 1
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#ifdef UART4
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if (RX_DMA.uart == UART4) DMAMUX1_Channel2->CCR |= DMA_REQUEST_UART4_RX; // DMA1, Stream 2
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#endif
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#ifdef USART4
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if (RX_DMA.uart == USART4) DMAMUX1_Channel2->CCR |= DMA_REQUEST_USART4_RX; // DMA1, Stream 2
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#endif
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#ifdef UART5
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if (RX_DMA.uart == UART5) DMAMUX1_Channel0->CCR |= DMA_REQUEST_UART5_RX; // DMA1, Stream 0
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#endif
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#ifdef USART6
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if (RX_DMA.uart == USART6) DMAMUX1_Channel9->CCR |= DMA_REQUEST_USART6_RX; // DMA2, Stream 1
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#endif
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#endif // !STM32H7xx
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// Configure DMA
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//RX_DMA.dma_streamRX->CR |= DMA_MBURST_SINGLE; // DMA stream Memory Burst transfer: single transfer = 0b00
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//RX_DMA.dma_streamRX->CR |= DMA_PBURST_SINGLE; // DMA stream Peripheral Burst transfer: single transfer = 0b00
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#if ENABLED(STM32H7xx)
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RX_DMA.dma_streamRX->CR |= DMA_SxCR_TRBUFF; // DMA stream Transfer handle bufferable (required for UART/USART)
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#endif
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//RX_DMA.dma_streamRX->CR &= ~DMA_SxCR_CT; // DMA stream Current Target (only in double buffer mode)
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//RX_DMA.dma_streamRX->CR &= ~DMA_SxCR_DBM; // DMA stream Double Buffer Mode
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//RX_DMA.dma_streamRX->CR |= DMA_PRIORITY_LOW; // DMA stream Priority Level Low = 0b00
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//RX_DMA.dma_streamRX->CR &= ~DMA_SxCR_PINCOS; // DMA stream Peripheral Increment Offset Size
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//RX_DMA.dma_streamRX->CR &= ~DMA_SxCR_MSIZE; // DMA stream Memory data Size: 8 bit = 0b00
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//RX_DMA.dma_streamRX->CR &= ~DMA_SxCR_PSIZE; // DMA stream Peripheral data Size: 8 bit = 0b00
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RX_DMA.dma_streamRX->CR |= DMA_SxCR_MINC; // DMA stream Memory Increment enable
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//RX_DMA.dma_streamRX->CR &= ~DMA_SxCR_PINC; // DMA stream Peripheral increment
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RX_DMA.dma_streamRX->CR |= DMA_SxCR_CIRC; // DMA stream Circular mode enable
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//RX_DMA.dma_streamRX->CR |= DMA_PERIPH_TO_MEMORY; // DMA stream transfer Direction: Peripheral-to-memory = b00
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//RX_DMA.dma_streamRX->CR &= ~DMA_SxCR_PFCTRL; // DMA stream Peripheral Flow Controller: DMA = 0
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//RX_DMA.dma_streamRX->CR &= ~DMA_SxCR_TCIE; // DMA stream Transfer Complete Interrupt
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//RX_DMA.dma_streamRX->CR &= ~DMA_SxCR_HTIE; // DMA stream Half Transfer Interrupt
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//RX_DMA.dma_streamRX->CR &= ~DMA_SxCR_TEIE; // DMA stream Transfer Error Interrupt
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//RX_DMA.dma_streamRX->CR &= ~DMA_SxCR_DMEIE; // DMA stream Direct Mode Error Interrupt
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RX_DMA.dma_streamRX->CR |= DMA_SxCR_EN; // DMA stream Enable
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// Configure UART/USART
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RX_DMA.uart->CR3 |= USART_CR3_DMAR; // UART DMA Receiver
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RX_DMA.uart->CR1 |= USART_CR1_TE; // UART Transmitter Enable
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RX_DMA.uart->CR1 |= USART_CR1_RE; // UART Receiver Enable
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RX_DMA.uart->CR1 |= USART_CR1_UE; // UART Enable
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}
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#endif // STM32F2xx || STM32F4xx || STM32F7xx
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#endif // STM32F2xx || STM32F4xx || STM32F7xx || STM32H7xx
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#if ANY(STM32F0xx, STM32F1xx)
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void HAL_HardwareSerial::Serial_DMA_Read_Enable() {
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||||
RCC_AHBPeriphClockCmd(RX_DMA.dma_rcc, ENABLE); // enable DMA clock
|
||||
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||||
RX_DMA.dma_channelRX->CPAR = (uint32_t)(&RX_DMA.uart->DR); // RX peripheral address (usart)
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RX_DMA.dma_channelRX->CMAR = (uint32_t)_serial.rx_buff; // RX destination address (memory)
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||||
RX_DMA.dma_channelRX->CNDTR = RX_BUFFER_SIZE; // RX buffer size
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||||
if (RX_DMA.DMA_ID == 1)
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||||
__HAL_RCC_DMA1_CLK_ENABLE(); // enable DMA1 clock
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||||
else
|
||||
__HAL_RCC_DMA2_CLK_ENABLE(); // enable DMA2 clock
|
||||
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||||
RX_DMA.dma_channelRX->CCR = 0; // RX channel selection, set to 0 all the other CR bits
|
||||
RX_DMA.dma_channelRX->CCR &= ~USART_CR1_UE; // DMA stream clear/disable
|
||||
while (RX_DMA.dma_channelRX->CCR & DMA_CCR_EN) { /* just wait for DMA to complete */ }
|
||||
|
||||
RX_DMA.dma_channelRX->CCR |= (3<<12); // RX priority level: Very High
|
||||
// Clear/disable UART and DMA
|
||||
RX_DMA.uart->CR1 = 0; // UART clear CR1, disable DMA
|
||||
|
||||
//RX_DMA.dma_channelRX->CCR &= ~(1<<10); // RX memory data size: 8 bit
|
||||
//RX_DMA.dma_channelRX->CCR &= ~(1<<8); // RX peripheral data size: 8 bit
|
||||
RX_DMA.dma_channelRX->CCR |= (1<<7); // RX memory increment mode
|
||||
//RX_DMA.dma_channelRX->CCR &= ~(1<<6); // RX peripheral no increment mode
|
||||
RX_DMA.dma_channelRX->CCR |= (1<<5); // RX circular mode enabled
|
||||
//RX_DMA.dma_channelRX->CCR &= ~(1<<4); // RX data transfer direction: Peripheral-to-memory
|
||||
// Configure DMA
|
||||
|
||||
RX_DMA.uart->CR3 |= (1<<6); // enable DMA receiver (DMAR)
|
||||
RX_DMA.dma_channelRX->CCR |= (1<<0); // RX enable DMA
|
||||
#ifdef STM32F0xx
|
||||
RX_DMA.dma_channelRX->CPAR = (uint32_t)(&RX_DMA.uart->RDR); // DMA channel Peripheral Address Register = USART Data Register
|
||||
#else
|
||||
RX_DMA.dma_channelRX->CPAR = (uint32_t)(&RX_DMA.uart->DR); // DMA channel Peripheral Address Register = USART Data Register
|
||||
#endif
|
||||
|
||||
RX_DMA.dma_channelRX->CMAR = (uint32_t)_serial.rx_buff; // DMA channel Memory Address Register
|
||||
RX_DMA.dma_channelRX->CNDTR = RX_BUFFER_SIZE; // DMA channel Number of Data Transfer Register
|
||||
//RX_DMA.dma_channelRX->CCR |= (0b00 << DMA_CCR_PL_Pos); // DMA channel Priority Level: Low = 0b00
|
||||
//RX_DMA.dma_channelRX->CCR &= ~DMA_CCR_MSIZE; // DMA channel Data Size: 8 bit = 0
|
||||
//RX_DMA.dma_channelRX->CCR &= ~DMA_CCR_PSIZE; // DMA channel Peripheral data size: 8 bit = 0
|
||||
RX_DMA.dma_channelRX->CCR |= DMA_CCR_MINC; // DMA channel Memory Increment enable
|
||||
//RX_DMA.dma_channelRX->CCR &= ~DMA_CCR_PINC; // DMA channel Peripheral Increment disable
|
||||
RX_DMA.dma_channelRX->CCR |= DMA_CCR_CIRC; // DMA channel Circular mode enable
|
||||
//RX_DMA.dma_channelRX->CCR &= ~DMA_CCR_DIR; // DMA channel Data Transfer direction: 0=Read peripheral, 1=Read memory
|
||||
//RX_DMA.dma_channelRX->CCR &= ~DMA_CCR_TEIE; // DMA channel Transfer Error Interrupt
|
||||
//RX_DMA.dma_channelRX->CCR &= ~DMA_CCR_HTIE; // DMA channel Half Transfer Interrupt
|
||||
//RX_DMA.dma_channelRX->CCR &= ~DMA_CCR_TCIE; // DMA channel Transfer Complete Interrupt
|
||||
RX_DMA.dma_channelRX->CCR |= DMA_CCR_EN; // DMA channel enable
|
||||
|
||||
// Configure UART/USART
|
||||
RX_DMA.uart->CR3 |= USART_CR3_DMAR; // UART DMA Receiver enabled
|
||||
RX_DMA.uart->CR1 |= USART_CR1_TE; // UART Transmitter Enable
|
||||
RX_DMA.uart->CR1 |= USART_CR1_RE; // UART Receiver Enable
|
||||
RX_DMA.uart->CR1 |= USART_CR1_UE; // UART Enable
|
||||
}
|
||||
|
||||
#endif // STM32F0xx || STM32F1xx
|
||||
|
|
|
|||
|
|
@ -38,12 +38,10 @@
|
|||
|
||||
typedef struct {
|
||||
USART_TypeDef * uart;
|
||||
uint32_t dma_rcc;
|
||||
uint32_t DMA_ID; // DMA1=1; DM2=2; BDMA=3
|
||||
#if ANY(STM32F0xx, STM32F1xx) // F0 / F1
|
||||
DMA_TypeDef * dma_controller;
|
||||
DMA_Channel_TypeDef * dma_channelRX;
|
||||
#else // F2 / F4 / F7
|
||||
uint32_t dma_channel;
|
||||
#else // F2 / F4 / F7 / H7
|
||||
DMA_Stream_TypeDef * dma_streamRX;
|
||||
#endif
|
||||
} DMA_CFG;
|
||||
|
|
|
|||
|
|
@ -245,7 +245,7 @@ static_assert(COUNT(arm) == LOGICAL_AXES, "AXIS_RELATIVE_MODES must contain " _L
|
|||
#if ENABLED(SERIAL_DMA)
|
||||
#ifdef ARDUINO_ARCH_HC32
|
||||
// checks for HC32 are located in HAL/HC32/inc/SanityCheck.h
|
||||
#elif DISABLED(HAL_STM32) || NONE(STM32F0xx, STM32F1xx, STM32F2xx, STM32F4xx, STM32F7xx)
|
||||
#elif DISABLED(HAL_STM32) || NONE(STM32F0xx, STM32F1xx, STM32F2xx, STM32F4xx, STM32F7xx, STM32H7xx)
|
||||
#error "SERIAL_DMA is only available for some STM32 MCUs and requires HAL/STM32."
|
||||
#elif !defined(HAL_UART_MODULE_ENABLED) || defined(HAL_UART_MODULE_ONLY)
|
||||
#error "SERIAL_DMA requires STM32 platform HAL UART (without HAL_UART_MODULE_ONLY)."
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue